Hello All,
We are currently working in the DM355 Davinci processor based customized
board. We have five I2C slave devices in the board. Out of the five
slave devices, one device needs the pixel cloclk/VCLK output from the
Davinci processor.
In order to generate the VCLK, we have to enable the VPSS SYS CLK Video
Encoder Clock and also the Video Control register clock in the VPBE
module.
VPSS SYS CLK is defined in the System control module data sheet. If we
enable this clock, the I2C data line goes low and the i2c communication
is getting failed in the board. If we are not setting this clock the i2c
communication is working fine.
Is there any register that links the Video Encoder Clock enable bit and
the I2C data line?
Setting the VPSS SYS CLOCK value to 0x08, causes this issue. Is there
any thing that could be at board level?
We don't think that there exist a relationship between the i2c data line
and the VPSS Video Encoder clock line. How this clock setting affects
the data line?
If someone faced the similar issue, please reply.
Thanks a lot in advance.
Thanks,
Prabha.
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