On Wednesday 10 December 2008, Felipe Balbi wrote: > > > The NAND device that comes with the DM355 EVM requires another > > resource here for the second NAND chip select, to be able to > > use the 2GB space. Has this configuration been tested on the EVM? > > As I understood from the documentation you use either one or the other. > They even have different width. CE0 uses 8bit and CE1 uses 16bit. If > it's really needed to pass both, an update patch is welcome.
Both use CE0 ... it's just that a bit of external logic morphs different chunks of the CE0 address space into selects for the two halves of that 2 GB chip. Sheet 12 of DM355 EVM schematics shows U4 and U5 combining CE0 and A12 to produce nNANDCE and nNANDCE2 ... :) I'd think the normal way to treat that would be to package it as two separate NAND devices ... which, in a sense, it is. Now, if you look at sheet 4 of the schematics you'll notice that a LED, DS22, is hooked up to GPIO61 which is glued to A7 (and ISTR must not be unmuxed). If you were really clever, I'd hope you would be able to make that serve as an activity light, to show when either NAND bank was being accessed. ;) - Dave _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
