Troy Kisky <[email protected]> writes:
> Currently, the aic33 codec is set to use I2S mode
> and the cpu is set to use dsp_b mode. Although,
> this seems to work if the codec is master. It is
> very confusing. Change both codec and cpu to
> use dsp_a mode.
>
> Signed-off-by: Troy Kisky <[email protected]>
>
> Kevin,
>
> I'm starting to split the patch apart to see where it goes
> wrong. Can you test this one?
On top of the current HEAD, I still here the pop, but don't hear any
audio.
If apply your 2 earlier patches
[PATCH 1/3] ARM: DaVinci: dma: don't clear link on stop yet
[PATCH 2/3] ARM: DaVinci: dma: move EXPORT immediately below function
And then this patch, I can hear audio again, but is very noisy
compared to without this patch.
Kevin
> diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
> index cff276e..3a83389 100644
> --- a/sound/soc/codecs/tlv320aic3x.c
> +++ b/sound/soc/codecs/tlv320aic3x.c
> @@ -871,7 +871,7 @@ static int aic3x_set_dai_fmt(struct snd_soc_dai
> *codec_dai,
> SND_SOC_DAIFMT_INV_MASK)) {
> case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
> break;
> - case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
> + case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
> iface_breg |= (0x01 << 6);
> break;
> case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
> diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
> index 24f1697..ba36ac3 100644
> --- a/sound/soc/davinci/davinci-evm.c
> +++ b/sound/soc/davinci/davinci-evm.c
> @@ -31,6 +31,9 @@
>
> #define EVM_CODEC_CLOCK 22579200
>
> +#define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_A | \
> + SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF)
> +
> static int evm_hw_params(struct snd_pcm_substream *substream,
> struct snd_pcm_hw_params *params)
> {
> @@ -40,14 +43,12 @@ static int evm_hw_params(struct snd_pcm_substream
> *substream,
> int ret = 0;
>
> /* set codec DAI configuration */
> - ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
> - SND_SOC_DAIFMT_CBM_CFM);
> + ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
> if (ret < 0)
> return ret;
>
> /* set cpu DAI configuration */
> - ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM |
> - SND_SOC_DAIFMT_IB_NF);
> + ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT);
> if (ret < 0)
> return ret;
>
> diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
> index ca2a50a..3c81946 100644
> --- a/sound/soc/davinci/davinci-i2s.c
> +++ b/sound/soc/davinci/davinci-i2s.c
> @@ -219,59 +219,82 @@ static int davinci_i2s_startup(struct snd_pcm_substream
> *substream)
> return 0;
> }
>
> +#define DEFAULT_BITPERSAMPLE 16
> +
> static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
> unsigned int fmt)
> {
> struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
> - u32 w;
> -
> + unsigned int pcr;
> + unsigned int srgr;
> + unsigned rcr;
> + unsigned xcr;
> + srgr = DAVINCI_MCBSP_SRGR_FSGM |
> + DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
> + DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
> +
> + /* set master/slave audio interface */
> switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> case SND_SOC_DAIFMT_CBS_CFS:
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
> - DAVINCI_MCBSP_PCR_FSXM |
> - DAVINCI_MCBSP_PCR_FSRM |
> - DAVINCI_MCBSP_PCR_CLKXM |
> - DAVINCI_MCBSP_PCR_CLKRM);
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
> - DAVINCI_MCBSP_SRGR_FSGM);
> + /* cpu is master */
> + pcr = DAVINCI_MCBSP_PCR_FSXM |
> + DAVINCI_MCBSP_PCR_FSRM |
> + DAVINCI_MCBSP_PCR_CLKXM |
> + DAVINCI_MCBSP_PCR_CLKRM;
> break;
> case SND_SOC_DAIFMT_CBM_CFS:
> /* McBSP CLKR pin is the input for the Sample Rate Generator.
> * McBSP FSR and FSX are driven by the Sample Rate Generator. */
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
> - DAVINCI_MCBSP_PCR_SCLKME |
> - DAVINCI_MCBSP_PCR_FSXM |
> - DAVINCI_MCBSP_PCR_FSRM);
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
> - DAVINCI_MCBSP_SRGR_FSGM);
> + pcr = DAVINCI_MCBSP_PCR_SCLKME |
> + DAVINCI_MCBSP_PCR_FSXM |
> + DAVINCI_MCBSP_PCR_FSRM;
> break;
> case SND_SOC_DAIFMT_CBM_CFM:
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
> + /* codec is master */
> + pcr = 0;
> break;
> default:
> + printk(KERN_ERR "%s:bad master\n", __func__);
> return -EINVAL;
> }
>
> switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
> case SND_SOC_DAIFMT_IB_NF:
> - w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
> - MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
> - DAVINCI_MCBSP_PCR_CLKRP, 1);
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
> + /* CLKRP Receive clock polarity,
> + * 1 - sampled on rising edge of CLKR
> + * valid on rising edge
> + * CLKXP Transmit clock polarity,
> + * 1 - clocked on falling edge of CLKX
> + * valid on rising edge
> + * FSRP Receive frame sync pol, 0 - active high
> + * FSXP Transmit frame sync pol, 0 - active high
> + */
> + pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
> break;
> case SND_SOC_DAIFMT_NB_IF:
> - w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
> - MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
> - DAVINCI_MCBSP_PCR_FSRP, 1);
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
> + /* CLKRP Receive clock polarity,
> + * 0 - sampled on falling edge of CLKR
> + * valid on falling edge
> + * CLKXP Transmit clock polarity,
> + * 0 - clocked on rising edge of CLKX
> + * valid on falling edge
> + * FSRP Receive frame sync pol, 1 - active low
> + * FSXP Transmit frame sync pol, 1 - active low
> + */
> + pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
> break;
> case SND_SOC_DAIFMT_IB_IF:
> - w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
> - MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
> - DAVINCI_MCBSP_PCR_CLKRP |
> - DAVINCI_MCBSP_PCR_FSXP |
> - DAVINCI_MCBSP_PCR_FSRP, 1);
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
> + /* CLKRP Receive clock polarity,
> + * 1 - sampled on rising edge of CLKR
> + * valid on rising edge
> + * CLKXP Transmit clock polarity,
> + * 1 - clocked on falling edge of CLKX
> + * valid on rising edge
> + * FSRP Receive frame sync pol, 1 - active low
> + * FSXP Transmit frame sync pol, 1 - active low
> + */
> + pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
> + DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
> break;
> case SND_SOC_DAIFMT_NB_NF:
> break;
> @@ -279,28 +302,24 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai
> *cpu_dai,
> return -EINVAL;
> }
>
> + /* interface format */
> + rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
> + xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
> switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> - case SND_SOC_DAIFMT_RIGHT_J:
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
> - DAVINCI_MCBSP_RCR_RFRLEN1(1) |
> - DAVINCI_MCBSP_RCR_RDATDLY(0));
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
> - DAVINCI_MCBSP_XCR_XFRLEN1(1) |
> - DAVINCI_MCBSP_XCR_XDATDLY(0) |
> - DAVINCI_MCBSP_XCR_XFIG);
> + case SND_SOC_DAIFMT_DSP_A:
> break;
> - case SND_SOC_DAIFMT_I2S:
> - default:
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
> - DAVINCI_MCBSP_RCR_RFRLEN1(1) |
> - DAVINCI_MCBSP_RCR_RDATDLY(1));
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
> - DAVINCI_MCBSP_XCR_XFRLEN1(1) |
> - DAVINCI_MCBSP_XCR_XDATDLY(1) |
> - DAVINCI_MCBSP_XCR_XFIG);
> + case SND_SOC_DAIFMT_DSP_B:
> + rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
> + xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
> break;
> + default:
> + printk(KERN_ERR "%s:bad format\n", __func__);
> + return -EINVAL;
> }
> -
> + davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
> + davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
> + davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
> + davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
> return 0;
> }
>
> @@ -325,12 +344,10 @@ static int davinci_i2s_hw_params(struct
> snd_pcm_substream *substream,
> }
>
> i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
> - w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
> + w = DAVINCI_MCBSP_SRGR_FSGM;
> MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
> - davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
>
> i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
> - w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
> MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
> davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
>
> --
> 1.5.4.3
>
>
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