On Friday 19 December 2008, Sudhakar Rajashekhara wrote: > Generalizes dm644x pinmux. > > The existing pinmux layer works only when the PINMUX register has single bit > field to enable the secondary function. DM646x can support secondary as well > as tertiary pin functions. This new pinmux layer is similar to the one being > used by OMAP architecture. > > Checkpatch script reports a false positive error at line no.465 of this patch. > > This patch is based on the work originally done by Vladimir Barinov, when he > was in MontaVista. > > Signed-off-by: Sudhakar Rajashekhara <[email protected]>
Acked-by: David Brownell <[email protected]> > --- > arch/arm/mach-davinci/Kconfig | 25 ++++ > arch/arm/mach-davinci/Makefile | 4 +- > arch/arm/mach-davinci/include/mach/mux.h | 194 > ++++++++++++++++++++++-------- > arch/arm/mach-davinci/io.c | 2 + > arch/arm/mach-davinci/mux.c | 98 +++++++++++++--- > arch/arm/mach-davinci/mux_cfg.c | 136 +++++++++++++++++++++ > arch/arm/mach-davinci/psc.c | 31 +++--- > drivers/mtd/nand/davinci_nand.c | 20 ++-- > 8 files changed, 413 insertions(+), 97 deletions(-) > create mode 100644 arch/arm/mach-davinci/mux_cfg.c > > diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig > index f82e6f4..20e55ea 100644 > --- a/arch/arm/mach-davinci/Kconfig > +++ b/arch/arm/mach-davinci/Kconfig > @@ -50,6 +50,31 @@ config MACH_DAVINCI_SFFSDR > Say Y here to select the Lyrtech Small Form Factor > Software Defined Radio (SFFSDR) board. > > +config DAVINCI_MUX > + bool "DAVINCI multiplexing support" > + depends on ARCH_DAVINCI > + default y > + help > + Pin multiplexing support for DAVINCI boards. If your bootloader > + sets the multiplexing correctly, say N. Otherwise, or if unsure, > + say Y. > + > +config DAVINCI_MUX_DEBUG > + bool "Multiplexing debug output" > + depends on DAVINCI_MUX > + help > + Makes the multiplexing functions print out a lot of debug info. > + This is useful if you want to find out the correct values of the > + multiplexing registers. > + > +config DAVINCI_MUX_WARNINGS > + bool "Warn about pins the bootloader didn't set up" > + depends on DAVINCI_MUX > + help > + Choose Y here to warn whenever driver initialization logic needs > + to change the pin multiplexing setup. When there are no warnings > + printed, it's safe to deselect DAVINCI_MUX for your product. > + > config DAVINCI_RESET_CLOCKS > bool "Reset unused clocks during boot" > depends on ARCH_DAVINCI > diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile > index 2a339db..24a9195 100644 > --- a/arch/arm/mach-davinci/Makefile > +++ b/arch/arm/mach-davinci/Makefile > @@ -5,7 +5,9 @@ > > # Common objects > obj-y := time.o irq.o clock.o serial.o io.o id.o > psc.o \ > - gpio.o mux.o devices.o usb.o dma.o common.o iram.o > + gpio.o devices.o usb.o dma.o common.o iram.o > + > +obj-$(CONFIG_DAVINCI_MUX) += mux.o mux_cfg.o > > # Board specific > obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o > diff --git a/arch/arm/mach-davinci/include/mach/mux.h > b/arch/arm/mach-davinci/include/mach/mux.h > index 9e7cf69..cfe59cd 100644 > --- a/arch/arm/mach-davinci/include/mach/mux.h > +++ b/arch/arm/mach-davinci/include/mach/mux.h > @@ -1,60 +1,152 @@ > /* > - * DaVinci pin multiplexing defines > + * Table of the DAVINCI register configurations for the PINMUX combinations > * > * Author: Vladimir Barinov, MontaVista Software, Inc. <[email protected]> > * > + * Based on linux/include/asm-arm/arch-omap/mux.h: > + * Copyright (C) 2003 - 2005 Nokia Corporation > + * > + * Written by Tony Lindgren > + * > * 2007 (c) MontaVista Software, Inc. This file is licensed under > * the terms of the GNU General Public License version 2. This program > * is licensed "as is" without any warranty of any kind, whether express > * or implied. > + * > + * Copyright (C) 2008 Texas Instruments. > */ > -#ifndef __ASM_ARCH_MUX_H > -#define __ASM_ARCH_MUX_H > - > -/* System control register offsets */ > -#define PINMUX0 0x00 > -#define PINMUX1 0x04 > - > -/* System control register bits */ > -#define DAVINCI_MUX_AEAW0 0 > -#define DAVINCI_MUX_AEAW1 1 > -#define DAVINCI_MUX_AEAW2 2 > -#define DAVINCI_MUX_AEAW3 3 > -#define DAVINCI_MUX_AEAW4 4 > -#define DAVINCI_MUX_AECS4 10 > -#define DAVINCI_MUX_AECS5 11 > -#define DAVINCI_MUX_VLYNQWD0 12 > -#define DAVINCI_MUX_VLYNQWD1 13 > -#define DAVINCI_MUX_VLSCREN 14 > -#define DAVINCI_MUX_VLYNQEN 15 > -#define DAVINCI_MUX_HDIREN 16 > -#define DAVINCI_MUX_ATAEN 17 > -#define DAVINCI_MUX_RGB666 22 > -#define DAVINCI_MUX_RGB888 23 > -#define DAVINCI_MUX_LOEEN 24 > -#define DAVINCI_MUX_LFLDEN 25 > -#define DAVINCI_MUX_CWEN 26 > -#define DAVINCI_MUX_CFLDEN 27 > -#define DAVINCI_MUX_HPIEN 29 > -#define DAVINCI_MUX_1394EN 30 > -#define DAVINCI_MUX_EMACEN 31 > - > -#define DAVINCI_MUX_LEVEL2 32 > -#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) > -#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) > -#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) > -#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) > -#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) > -#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) > -#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) > -#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) > -#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) > -#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) > -#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) > -#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) > -#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) > -#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) > - > -extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); > - > -#endif /* __ASM_ARCH_MUX_H */ > + > +#ifndef __INC_MACH_MUX_H > +#define __INC_MACH_MUX_H > + > +#include <mach/dm644x.h> > + > +/* System module registers */ > +#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) > +#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) > +/* dm355 only */ > +#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) > +#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) > +#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) > + > +struct mux_config { > + char *name; > + const char *mux_reg_name; > + const unsigned int mux_reg; > + const unsigned char mask_offset; > + const unsigned char mask; > + const unsigned char mode; > + bool debug; > +}; > + > +enum davinci_dm644x_index { > + /* ATA and HDDIR functions */ > + DM644X_HDIREN, > + DM644X_ATAEN, > + DM644X_ATAEN_DISABLE, > + > + /* HPI functions */ > + DM644X_HPIEN_DISABLE, > + > + /* AEAW functions */ > + DM644X_AEAW, > + > + /* Memory Stick */ > + DM644X_MSTK, > + > + /* I2C */ > + DM644X_I2C, > + > + /* ASP function */ > + DM644X_MCBSP, > + > + /* PWM0 */ > + DM644X_PWM0, > + > + /* PWM1 */ > + DM644X_PWM1, > + > + /* PWM2 */ > + DM644X_PWM2, > + > + /* VLYNQ function */ > + DM644X_VLYNQEN, > + DM644X_VLSCREN, > + DM644X_VLYNQWD, > + > + /* EMAC and MDIO function */ > + DM644X_EMACEN, > + > + /* GPIO3V[0:16] pins */ > + DM644X_GPIO3V, > + > + /* GPIO pins */ > + DM644X_GPIO0, > + DM644X_GPIO3, > + DM644X_GPIO43_44, > + DM644X_GPIO46_47, > + > + /* VPBE */ > + DM644X_RGB666, > + > + /* LCD */ > + DM644X_LOEEN, > + DM644X_LFLDEN, > +}; > + > +enum davinci_dm646x_index { > + /* ATA function */ > + DM646X_ATAEN, > + > + /* AUDIO Clock */ > + DM646X_AUDCK1, > + DM646X_AUDCK0, > +}; > + > +enum davinci_dm355_index { > + /* MMC/SD 0 */ > + DM355_MMCSD0, > + > + /* MMC/SD 1 */ > + DM355_SD1_CLK, > + DM355_SD1_CMD, > + DM355_SD1_DATA3, > + DM355_SD1_DATA2, > + DM355_SD1_DATA1, > + DM355_SD1_DATA0, > + > + /* I2C */ > + DM355_I2C_SDA, > + DM355_I2C_SCL, > + > + /* ASP function */ > + DM355_MCBSP0_BDX, > + DM355_MCBSP0_X, > + DM355_MCBSP0_BFSX, > + DM355_MCBSP0_BDR, > + DM355_MCBSP0_R, > + DM355_MCBSP0_BFSR, > + > + /* SPI0 */ > + DM355_SPI0_SDI, > + DM355_SPI0_SDENA0, > + DM355_SPI0_SDENA1, > +}; > + > +#ifdef CONFIG_DAVINCI_MUX > +/* setup pin muxing */ > +extern void davinci_mux_init(void); > +extern int davinci_mux_register(const struct mux_config *pins, > + unsigned long size); > +extern int davinci_cfg_reg(unsigned long reg_cfg); > +#else > +/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ > +static inline void davinci_mux_init(void) > +{ > +} > +static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } > +#endif > + > +extern void (*davinci_pinmux_setup)(unsigned int id); > + > +#endif /* __INC_MACH_MUX_H */ > diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c > index 299515f..c493889 100644 > --- a/arch/arm/mach-davinci/io.c > +++ b/arch/arm/mach-davinci/io.c > @@ -18,6 +18,7 @@ > > #include <asm/mach/map.h> > #include <mach/clock.h> > +#include <mach/mux.h> > > extern void davinci_check_revision(void); > > @@ -53,5 +54,6 @@ void __init davinci_map_common_io(void) > > void __init davinci_init_common_hw(void) > { > + davinci_mux_init(); > davinci_clk_init(); > } > diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c > index be33108..7f670f0 100644 > --- a/arch/arm/mach-davinci/mux.c > +++ b/arch/arm/mach-davinci/mux.c > @@ -1,39 +1,103 @@ > /* > - * DaVinci pin multiplexing configurations > + * Utility to set the DAVINCI MUX register from a table in mux.h > * > * Author: Vladimir Barinov, MontaVista Software, Inc. <[email protected]> > * > + * Based on linux/arch/arm/plat-omap/mux.c: > + * Copyright (C) 2003 - 2005 Nokia Corporation > + * > + * Written by Tony Lindgren > + * > * 2007 (c) MontaVista Software, Inc. This file is licensed under > * the terms of the GNU General Public License version 2. This program > * is licensed "as is" without any warranty of any kind, whether express > * or implied. > + * > + * Copyright (C) 2008 Texas Instruments. > */ > #include <linux/io.h> > #include <linux/module.h> > #include <linux/spinlock.h> > > #include <mach/hardware.h> > - > #include <mach/mux.h> > > -static DEFINE_SPINLOCK(mux_lock); > +static const struct mux_config *mux_table; > +static unsigned long pin_table_sz; > > -void davinci_mux_peripheral(unsigned int mux, unsigned int enable) > +int __init davinci_mux_register(const struct mux_config *pins, > + unsigned long size) > { > - u32 pinmux, muxreg = PINMUX0; > + mux_table = pins; > + pin_table_sz = size; > + > + return 0; > +} > + > +/* > + * Sets the DAVINCI MUX register based on the table > + */ > +int __init_or_module davinci_cfg_reg(const unsigned long index) > +{ > + static DEFINE_SPINLOCK(mux_spin_lock); > + > + unsigned long flags; > + const struct mux_config *cfg; > + unsigned int reg_orig = 0, reg = 0; > + unsigned int mask, warn = 0; > + > + if (!mux_table) > + BUG(); > + > + if (index >= pin_table_sz) { > + printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", > + index, pin_table_sz); > + dump_stack(); > + return -ENODEV; > + } > + > + cfg = &mux_table[index]; > + > + if (cfg->name == NULL) { > + printk(KERN_ERR "No entry for the specified index\n"); > + return -ENODEV; > + } > + > + /* Check the mux register in question */ > + if (cfg->mux_reg) { > + unsigned tmp1, tmp2; > + > + spin_lock_irqsave(&mux_spin_lock, flags); > + reg_orig = davinci_readl(cfg->mux_reg); > + > + mask = (cfg->mask << cfg->mask_offset); > + tmp1 = reg_orig & mask; > + reg = reg_orig & ~mask; > + > + tmp2 = (cfg->mode << cfg->mask_offset); > + reg |= tmp2; > + > + if (tmp1 != tmp2) > + warn = 1; > + > + davinci_writel(reg, cfg->mux_reg); > + spin_unlock_irqrestore(&mux_spin_lock, flags); > + } > + > + if (warn) { > +#ifdef CONFIG_DAVINCI_MUX_WARNINGS > + printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); > +#endif > + } > > - if (mux >= DAVINCI_MUX_LEVEL2) { > - muxreg = PINMUX1; > - mux -= DAVINCI_MUX_LEVEL2; > +#ifdef CONFIG_DAVINCI_MUX_DEBUG > + if (cfg->debug || warn) { > + printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name); > + printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n", > + cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); > } > +#endif > > - spin_lock(&mux_lock); > - pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg); > - if (enable) > - pinmux |= (1 << mux); > - else > - pinmux &= ~(1 << mux); > - davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg); > - spin_unlock(&mux_lock); > + return 0; > } > -EXPORT_SYMBOL(davinci_mux_peripheral); > +EXPORT_SYMBOL(davinci_cfg_reg); > diff --git a/arch/arm/mach-davinci/mux_cfg.c b/arch/arm/mach-davinci/mux_cfg.c > new file mode 100644 > index 0000000..39a55ab > --- /dev/null > +++ b/arch/arm/mach-davinci/mux_cfg.c > @@ -0,0 +1,136 @@ > +/* > + * DAVINCI pin multiplexing configurations > + * > + * Author: Vladimir Barinov, MontaVista Software, Inc. <[email protected]> > + * > + * Based on linux/arch/arm/mach-omap1/mux.c: > + * Copyright (C) 2003 - 2005 Nokia Corporation > + * > + * Written by Tony Lindgren > + * > + * 2007 (c) MontaVista Software, Inc. This file is licensed under > + * the terms of the GNU General Public License version 2. This program > + * is licensed "as is" without any warranty of any kind, whether express > + * or implied. > + * > + * Copyright (C) 2008 Texas Instruments. > + */ > + > +#include <linux/module.h> > +#include <linux/init.h> > + > +#include <mach/hardware.h> > +#include <mach/cpu.h> > +#include <mach/mux.h> > + > +#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ > +[soc##_##desc] = { \ > + .name = #desc, \ > + .debug = dbg, \ > + .mux_reg_name = "PINMUX"#muxreg, \ > + .mux_reg = PINMUX##muxreg, \ > + .mask_offset = mode_offset, \ > + .mask = mode_mask, \ > + .mode = mux_mode, \ > + }, > + > +/* > + * soc description mux mode mode mux dbg > + * reg offset mask mode > + */ > +static const struct mux_config davinci_dm644x_pins[] = { > +MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) > +MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) > +MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) > + > +MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) > + > +MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) > + > +MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) > + > +MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) > + > +MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) > + > +MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) > + > +MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) > + > +MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) > + > +MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) > +MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) > +MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) > + > +MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) > + > +MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) > + > +MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) > +MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) > +MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) > +MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) > + > +MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) > + > +MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) > +MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) > +}; > + > +/* > + * soc description mux mode mode mux dbg > + * reg offset mask mode > + */ > +static const struct mux_config davinci_dm646x_pins[] = { > +MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) > + > +MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) > + > +MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) > +}; > + > +/* > + * soc description mux mode mode mux dbg > + * reg offset mask mode > + */ > +static const struct mux_config davinci_dm355_pins[] = { > +MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) > + > +MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) > +MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false) > +MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false) > +MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false) > +MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false) > +MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false) > + > +MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false) > +MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false) > + > +MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) > +MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) > +MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) > +MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) > +MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) > +MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) > + > +MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) > +MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) > +MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) > +}; > + > +void __init davinci_mux_init(void) > +{ > + if (cpu_is_davinci_dm644x()) > + davinci_mux_register(davinci_dm644x_pins, > + ARRAY_SIZE(davinci_dm644x_pins)); > + else if (cpu_is_davinci_dm646x()) > + davinci_mux_register(davinci_dm646x_pins, > + ARRAY_SIZE(davinci_dm646x_pins)); > + else if (cpu_is_davinci_dm355()) > + davinci_mux_register(davinci_dm355_pins, > + ARRAY_SIZE(davinci_dm355_pins)); > + else > + printk(KERN_ERR "PSC: DaVinci variant not supported\n"); > +} > + > diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c > index 804488b..ce4a17b 100644 > --- a/arch/arm/mach-davinci/psc.c > +++ b/arch/arm/mach-davinci/psc.c > @@ -48,8 +48,8 @@ static void dm6446_psc_mux(unsigned int id) > { > switch (id) { > case DAVINCI_LPSC_ATA: > - davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); > - davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); > + davinci_cfg_reg(DM644X_HDIREN); > + davinci_cfg_reg(DM644X_ATAEN); > break; > case DAVINCI_LPSC_MMC_SD: > /* VDD power manupulations are done in U-Boot for CPMAC > @@ -57,13 +57,13 @@ static void dm6446_psc_mux(unsigned int id) > */ > /*Set up the pull regiter for MMC */ > davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN); > - davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0); > + davinci_cfg_reg(DM644X_MSTK); > break; > case DAVINCI_LPSC_I2C: > - davinci_mux_peripheral(DAVINCI_MUX_I2C, 1); > + davinci_cfg_reg(DM644X_I2C); > break; > case DAVINCI_LPSC_McBSP: > - davinci_mux_peripheral(DAVINCI_MUX_ASP, 1); > + davinci_cfg_reg(DM644X_MCBSP); > break; > default: > break; > @@ -88,11 +88,12 @@ static void dm355_psc_mux(unsigned int id) > switch (id) { > case DM355_LPSC_MMC_SD1: /* MMC1 */ > /* expose DATA[0..3], CMD, CLK */ > - tmp = davinci_readl(DM355_ARM_PINMUX3); > - tmp &= ~((3 << 14) | (3 << 12) | (3 << 10) | (3 << 8)); > - tmp |= (1 << 14) | (1 << 12) | (1 << 10) | (1 << 8) > - | BIT(7) | BIT(6); > - davinci_writel(tmp, DM355_ARM_PINMUX3); > + davinci_cfg_reg(DM355_SD1_CLK); > + davinci_cfg_reg(DM355_SD1_CMD); > + davinci_cfg_reg(DM355_SD1_DATA3); > + davinci_cfg_reg(DM355_SD1_DATA2); > + davinci_cfg_reg(DM355_SD1_DATA1); > + davinci_cfg_reg(DM355_SD1_DATA0); > break; > case DM355_LPSC_McBSP1: /* ASP1 */ > /* our ASoC code currently doesn't use these IRQs */ > @@ -110,9 +111,7 @@ static void dm355_psc_mux(unsigned int id) > break; > case DAVINCI_LPSC_MMC_SD: /* MMC0 */ > /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ > - tmp = davinci_readl(DM355_ARM_PINMUX4); > - tmp &= ~BIT(2); > - davinci_writel(tmp, DM355_ARM_PINMUX4); > + davinci_cfg_reg(DM355_MMCSD0); > > /* support EMDA for MMC0 RX */ > tmp = davinci_readl(DM355_EDMA_EVTMUX); > @@ -124,9 +123,7 @@ static void dm355_psc_mux(unsigned int id) > * NOTE: SPIO_SDENA0 and/or SPIO_SDENA1 > * will need to be set too. > */ > - tmp = davinci_readl(DM355_ARM_PINMUX4); > - tmp &= ~BIT(1); > - davinci_writel(tmp, DM355_ARM_PINMUX4); > + davinci_cfg_reg(DM355_SPI0_SDI); > break; > } > } > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c > index 49bf37b..55e2eb5 100644 > --- a/drivers/mtd/nand/davinci_nand.c > +++ b/drivers/mtd/nand/davinci_nand.c > @@ -531,23 +531,19 @@ static void __init nand_dm6446evm_flash_init(struct > davinci_nand_info *info) > */ > if (machine_is_davinci_evm()) { > /* Check for correct pin mux, reconfigure if necessary */ > - tmp = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + PINMUX0); > + tmp = davinci_readl(PINMUX0); > > if ((tmp & 0x20020C1F) != 0x00000C1F) { > /* Disable HPI and ATA mux */ > - davinci_mux_peripheral(DAVINCI_MUX_HPIEN, 0); > - davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 0); > + davinci_cfg_reg(DM644X_HPIEN_DISABLE); > + davinci_cfg_reg(DM644X_ATAEN_DISABLE); > > /* Enable VLYNQ and AEAW */ > - davinci_mux_peripheral(DAVINCI_MUX_AEAW0, 1); > - davinci_mux_peripheral(DAVINCI_MUX_AEAW1, 1); > - davinci_mux_peripheral(DAVINCI_MUX_AEAW2, 1); > - davinci_mux_peripheral(DAVINCI_MUX_AEAW3, 1); > - davinci_mux_peripheral(DAVINCI_MUX_AEAW4, 1); > - davinci_mux_peripheral(DAVINCI_MUX_VLSCREN, 1); > - davinci_mux_peripheral(DAVINCI_MUX_VLYNQEN, 1); > - > - regval = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + > PINMUX0); > + davinci_cfg_reg(DM644X_AEAW); > + davinci_cfg_reg(DM644X_VLSCREN); > + davinci_cfg_reg(DM644X_VLYNQEN); > + > + regval = davinci_readl(PINMUX0); > > dev_warn(info->dev, "Warning: MUX config for NAND: Set > " \ > "PINMUX0 reg to 0x%08x, was 0x%08x, > should be done " \ > -- > 1.5.4.1 > > _______________________________________________ > Davinci-linux-open-source mailing list > [email protected] > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
