Deepika, If this is an interlaced solution that you are seeking, then this is a pretty straight set:
1. Disable the BT656 bit in the CCDC settings; 2. You will have to set a few bits in the CCDC registers for a 16 bit wide data path; configure the polarity settings for the hsync and vsync. I dont remember the exact registers as of now; but if you look up the ccdc_davinci driver file, you should be able to get those registers straight out in the config_ccdc_ycbcr function. And also make sure that your FID, field ID signal is connected. I believe the EVMs have this pin grounded; check up your schematics; for in interlaced settings, you wont get a full frame until the field ID gets toggled! Hope this helps! Cheers!
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