> On Wed, 3 Dec 2008 10:17:25 +0530 > Sudhakar Rajashekhara <[email protected]> wrote: > >> New PIN MUX layer support for TI DaVinci SoCs >> ... >> This patch adds a new pinmux layer for TI DaVinci SoC. The existing >> pinmux layer works only when the PINMUX register has single bit field >> to enable the secondary function. DM646x can support secondary as >> well as tertiary pin functions. This new pinmux layer is similar to >> the one being used by OMAP architecture. >> ... >> -/* System control register bits */ >> -#define DAVINCI_MUX_AEAW0 0 >> -#define DAVINCI_MUX_AEAW1 1 >> -#define DAVINCI_MUX_AEAW2 2 >> -#define DAVINCI_MUX_AEAW3 3 >> -#define DAVINCI_MUX_AEAW4 4 >> -#define DAVINCI_MUX_AECS4 10 >> -#define DAVINCI_MUX_AECS5 11 >> -#define DAVINCI_MUX_VLYNQWD0 12 >> -#define DAVINCI_MUX_VLYNQWD1 13 >> -#define DAVINCI_MUX_VLSCREN 14 >> -#define DAVINCI_MUX_VLYNQEN 15 >> -#define DAVINCI_MUX_HDIREN 16 >> -#define DAVINCI_MUX_ATAEN 17 >> -#define DAVINCI_MUX_RGB666 22 >> -#define DAVINCI_MUX_RGB888 23 >> -#define DAVINCI_MUX_LOEEN 24 >> -#define DAVINCI_MUX_LFLDEN 25 >> -#define DAVINCI_MUX_CWEN 26 >> -#define DAVINCI_MUX_CFLDEN 27 >> -#define DAVINCI_MUX_HPIEN 29 >> -#define DAVINCI_MUX_1394EN 30 >> -#define DAVINCI_MUX_EMACEN 31 >> - >> -#define DAVINCI_MUX_LEVEL2 32 >> -#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) >> -#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) >> -#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) > > How can I enable UART2 with the new architecture? > > don´t see any UART2 in the enum davinci_dm644x_index (mux.h) > > Hugo V.
You can add your own entries into davinci_dm644x_index in mux.h and add corresponding entries in davinci_dm644x_pins table in mux_cfg.c file. Regards, Sudahkar_______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
