From: David Brownell <[email protected]>
Minor tweaks:
- Bugfix handling of EVENTQ_DEFAULT ... recognize it, and
implement as EVENTQ_1 instead of reserved/illegal value
- Use the defined enum type internally
- Have MMC use TC1, as appropriate for "longer, nonreal-time
sensitive transfers" (per docs) ... instead of using TC0,
as for "urgent, small, real-time sensitive transfers".
Arguably, TC0 priority should be increased (to 0) to be
higher priority than the ARM ... matching "urgent" etc.
The added TCs on DM646x chips are still not recognized.
Signed-off-by: David Brownell <[email protected]>
---
arch/arm/mach-davinci/dma.c | 11 ++++++++---
drivers/mmc/host/davinci_mmc.c | 6 ++++--
2 files changed, 12 insertions(+), 5 deletions(-)
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -281,10 +281,14 @@ queue_priority_mapping[DAVINCI_EDMA_NUM_
/*****************************************************************************/
-static void map_dmach_queue(int ch_no, int queue_no)
+static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
{
int bit = (ch_no & 0x7) * 4;
+ /* default to low priority queue */
+ if (queue_no == EVENTQ_DEFAULT)
+ queue_no = EVENTQ_1;
+
queue_no &= 7;
edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3),
~(0x7 << bit), queue_no << bit);
@@ -547,7 +551,7 @@ static int __init davinci_dma_init(void)
* started by the codec engine will not cause audio defects.
*/
for (i = 0; i < DAVINCI_EDMA_NUM_DMACH; i++)
- map_dmach_queue(i, 1);
+ map_dmach_queue(i, EVENTQ_1);
i = 0;
/* Event queue to TC mapping */
@@ -581,7 +585,8 @@ arch_initcall(davinci_dma_init);
* @callback: optional; to be issued on DMA completion or errors
* @data: passed to callback
* @eventq_no: an EVENTQ_* constant, used to choose which Transfer
- * Controller (TC) executes requests using this channel
+ * Controller (TC) executes requests using this channel. Use
+ * EVENTQ_DEFAULT unless you really need a high priority queue.
*
* This allocates a DMA channel and its associated parameter RAM slot.
* The parameter RAM is initialized to hold a dummy transfer.
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -589,7 +589,8 @@ static int __init davinci_acquire_dma_ch
int r, i;
/* Acquire master DMA write channel */
- r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, EVENTQ_0);
+ r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
+ EVENTQ_DEFAULT);
if (r < 0) {
dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
"tx", r);
@@ -598,7 +599,8 @@ static int __init davinci_acquire_dma_ch
mmc_davinci_dma_setup(host, true, &host->tx_template);
/* Acquire master DMA read channel */
- r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, EVENTQ_0);
+ r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
+ EVENTQ_DEFAULT);
if (r < 0) {
dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
"rx", r);
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