David Brownell <[email protected]> writes: > From: David Brownell <[email protected]> > > Declare 4-bit ECC registers, as supported by AEMIF on DM355 and > various other chips. Such improved reliability will be nice, > when the NAND driver eventually supports it. > > Signed-off-by: David Brownell <[email protected]>
Thanks, pushing today. Kevin > --- > arch/arm/mach-davinci/include/mach/nand.h | 14 +++++++++++ > drivers/mtd/nand/davinci_nand.c | 34 ++++++++++++++++++++++++---- > drivers/mtd/nand/nand_bbt.c | 25 ++++++++++++++++++++ > 3 files changed, 69 insertions(+), 4 deletions(-) > > --- a/arch/arm/mach-davinci/include/mach/nand.h > +++ b/arch/arm/mach-davinci/include/mach/nand.h > @@ -37,6 +37,20 @@ > #define NANDFSR_OFFSET 0x64 > #define NANDF1ECC_OFFSET 0x70 > > +/* 4-bit ECC syndrome registers */ > +#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc > +#define NAND_4BIT_ECC1_OFFSET 0xc0 > +#define NAND_4BIT_ECC2_OFFSET 0xc4 > +#define NAND_4BIT_ECC3_OFFSET 0xc8 > +#define NAND_4BIT_ECC4_OFFSET 0xcc > +#define NAND_ERR_ADD1_OFFSET 0xd0 > +#define NAND_ERR_ADD2_OFFSET 0xd4 > +#define NAND_ERR_ERRVAL1_OFFSET 0xd8 > +#define NAND_ERR_ERRVAL2_OFFSET 0xdc > + > +/* NOTE: boards don't need to use these address bits > + * for ALE/CLE unless they support booting from NAND. > + */ > #define MASK_ALE 0x08 > #define MASK_CLE 0x10 > > > _______________________________________________ > Davinci-linux-open-source mailing list > [email protected] > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
