From: David Brownell <[email protected]> Subject: davinci_nand: clean up the A1CR hacks
The A1CR hacks aren't really needed on the DM355 EVM; NAND timings set by UBL (or whatever) are a bit slower than needed, but that's not too bad. Remove, but add a comment in board setup. For the DM6446 EVM, the problem is how to cope with re-jumpering in the default boot-from-NOR case. Boards modified to boot from NAND should already have A1CR timings set up. Comment this; for the moment it's a bit nasty to move this code to board setup. (And remove pointless AWRCC setting. The "Extended Wait" mode doesn't work with NAND chips.) Related -- make board-dm6446-evm.c warn about trying to make NAND and NOR coexist, and only set up one of them. Signed-off-by: David Brownell <[email protected]> --- arch/arm/mach-davinci/board-dm355-evm.c | 5 + arch/arm/mach-davinci/board-dm644x-evm.c | 6 +- drivers/mtd/nand/davinci_nand.c | 74 +++++------------------------ 3 files changed, 22 insertions(+), 63 deletions(-) --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -234,6 +234,11 @@ static __init void dm355_evm_init(void) evm_init_i2c(); davinci_serial_init(&uart_config); + /* NOTE: NAND flash timings set by the UBL are slower than + * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 + * but could be 0x0400008c. + */ + gpio_request(2, "usb_id_toggle"); gpio_direction_output(2, USB_ID_VALUE); /* irlml6401 switches over 1A in under 8 msec */ --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -646,8 +646,10 @@ static __init void davinci_evm_init(void if (HAS_NAND) { platform_device_register(&davinci_evm_nandflash_device); evm_leds[7].default_trigger = "nand-disk"; - } - if (HAS_NOR) + if (HAS_NOR) + pr_warning("WARNING: both NAND and NOR flash " + "are enabled; disable one of them.\n"); + } else if (HAS_NOR) platform_device_register(&davinci_evm_norflash_device); } --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -283,70 +283,18 @@ static int nand_davinci_dev_ready(struct return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); } -static void __init nand_dm355evm_flash_init(struct davinci_nand_info *info) -{ - u32 val, tmp; - - /* - * For AEMIFCLK at 108.0 MHz (9.26 nsec/tick) these timings: - * - have small (a few nsec) margins for pcb+socket delays - * - assume standard mode operations (not cache mode) - * - are WAY OFF for turnaround not gated by ARM instructions - * - * Write setup (tCS, tDS) min 15 nsec - * Write strobes (tWP) could be subsumed in setup - * - * Read setup (tCEA - tREA) min 5 nsec - * Read strobes (tRP) min 12 nsec - * - * Hold times (tALH, tCLH, tCH, tDH) min 5 nsec - * Read and write cycle times (tRC, tWC) min 25 nsec - * Turnaround (tWHR, tRHW) min 100 nsec - */ - val = 0 - | (0 << 31) /* selectStrobe normal mode */ - | (0 << 30) /* extWait mbz for NAND */ - - /* WRITE: */ - | (1 << 26) /* Setup 2 ticks (18 ns) */ - | (0 << 20) /* Strobe 1 tick (9 ns) */ - | (0 << 17) /* Hold 1 tick (9 ns) */ - - /* READ: */ - | (0 << 13) /* Setup 1 tick (9 ns) */ - | (1 << 7) /* Strobe 2 ticks (18 ns) */ - | (0 << 4) /* Hold 1 tick (9 ns) */ - - | (3 << 2) /* turnAround 3 ticks (TOO LOW) */ - | (0 << 0) /* asyncSize eight-bit bus */ - ; - - tmp = davinci_nand_readl(info, A1CR_OFFSET); - if (tmp != val) { - dev_dbg(info->dev, "NAND config: Set A1CR " - "to 0x%08x, was 0x%08x\n", val, tmp); - davinci_nand_writel(info, A1CR_OFFSET, val); - } -} - static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) { u32 regval, tmp; - regval = davinci_nand_readl(info, AWCCR_OFFSET); - regval |= 0x10000000; - davinci_nand_writel(info, AWCCR_OFFSET, regval); - - /*------------------------------------------------------------------* - * NAND FLASH CHIP TIMEOUT @ 459 MHz * - * * - * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * - * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * - * * - *------------------------------------------------------------------*/ + /* + * NAND FLASH timings @ PLL1 == 459 MHz + * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz + * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns + */ regval = 0 | (0 << 31) /* selectStrobe */ - | (0 << 30) /* extWait */ + | (0 << 30) /* extWait (never with NAND) */ | (1 << 26) /* writeSetup 10 ns */ | (3 << 20) /* writeStrobe 40 ns */ | (1 << 17) /* writeHold 10 ns */ @@ -503,9 +451,13 @@ static int __init nand_davinci_probe(str goto err_clk_enable; } - /* FIXME these don't belong here ... */ - if (machine_is_davinci_dm355_evm()) - nand_dm355evm_flash_init(info); + /* EMIF timings should normally be set by the boot loader, + * especially after boot-from-NAND. The *only* reason to + * have this special casing for the DM6446 EVM is to work + * with boot-from-NOR ... with CS0 manually re-jumpered + * (after startup) so it addresses the NAND flash, not NOR. + * Even for dev boards, that's unusually rude... + */ if (machine_is_davinci_evm()) nand_dm6446evm_flash_init(info); _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
