Kevin Hilman <[email protected]> writes:
> Updates from v1/v2:
> - add CLK_PSC flag (set at init for clks with 'lpsc' filled out)
> - blindly dropped the remaining boot-time PSC inits
> - more lowercase clock names, and removal of '_clk' suffix in strings
>
> and from Dave:
> - Add PSC_DSP flag for updating dm644x DSP and VICP clocks
> - When disabling unused clocks, avoid WARN() spewage
> - On dm355, list two more clocks
> - On dm64xx, list the DSP clocks too
> - Correct some LPSC definitions: remove invalid, define dm646x ARM
> - AEMIF shouldn't be "always enabled" on dm6446 (EVM may need NOR tweaks)
>
> Notes:
> - PWM[0,1] on dm6467 hang the system when disabled. Add the
> 'usecount = 1' workaround and 'REVISIT' comment.
>
> Overview
> - distinguish between PLL1- and PLL2-derived SYSCLKs
> - PLL-derived AUX ans bypass clocks are sourced
> before the multiplier and divider(s)
>
> TODO:
> - move the device-specific PSC init into <device>.c
>
> This was boot-tested on dm6446, dm355, dm6467 with a quick
> sanity check of /proc/davinci_clocks.
>
> With this, I think I"m ready to merge this unless there are any
> other problems. I'll handle the 'TODO' in another patch.
>
> Signed-off-by: Kevin Hilman <[email protected]>
Pushing today,
Kevin
> ---
> arch/arm/mach-davinci/board-dm355-evm.c | 7 +
> arch/arm/mach-davinci/board-dm644x-evm.c | 9 ++-
> arch/arm/mach-davinci/clock.c | 60 +++++++---
> arch/arm/mach-davinci/clock.h | 5 +-
> arch/arm/mach-davinci/devices.c | 4 +-
> arch/arm/mach-davinci/dm355.c | 204
> ++++++++++++++++++------------
> arch/arm/mach-davinci/dm644x.c | 183 ++++++++++++++++++++-------
> arch/arm/mach-davinci/dm646x.c | 143 +++++++++++++--------
> arch/arm/mach-davinci/include/mach/psc.h | 8 +-
> arch/arm/mach-davinci/psc.c | 16 ---
> arch/arm/mach-davinci/usb.c | 2 +-
> drivers/mtd/nand/davinci_nand.c | 7 +-
> sound/soc/davinci/davinci-i2s.c | 2 +-
> 13 files changed, 423 insertions(+), 227 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/board-dm355-evm.c
> b/arch/arm/mach-davinci/board-dm355-evm.c
> index f477933..8a0359e 100644
> --- a/arch/arm/mach-davinci/board-dm355-evm.c
> +++ b/arch/arm/mach-davinci/board-dm355-evm.c
> @@ -19,6 +19,7 @@
> #include <linux/i2c.h>
> #include <linux/io.h>
> #include <linux/gpio.h>
> +#include <linux/clk.h>
>
> #include <asm/setup.h>
> #include <asm/mach-types.h>
> @@ -225,10 +226,16 @@ static struct davinci_mmc_config dm355evm_mmc_config = {
>
> static __init void dm355_evm_init(void)
> {
> + struct clk *aemif;
> +
> gpio_request(1, "dm9000");
> gpio_direction_input(1);
> dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
>
> + aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
> + clk_enable(aemif);
> + clk_put(aemif);
> +
> platform_add_devices(davinci_evm_devices,
> ARRAY_SIZE(davinci_evm_devices));
> evm_init_i2c();
> diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c
> b/arch/arm/mach-davinci/board-dm644x-evm.c
> index a4ecf18..20ec961 100644
> --- a/arch/arm/mach-davinci/board-dm644x-evm.c
> +++ b/arch/arm/mach-davinci/board-dm644x-evm.c
> @@ -26,6 +26,7 @@
> #include <linux/mtd/physmap.h>
> #include <linux/io.h>
> #include <linux/phy.h>
> +#include <linux/clk.h>
>
> #include <asm/setup.h>
> #include <asm/mach-types.h>
> @@ -629,6 +630,12 @@ static int davinci_phy_fixup(struct phy_device *phydev)
>
> static __init void davinci_evm_init(void)
> {
> + struct clk *aemif_clk;
> +
> + aemif_clk = clk_get(NULL, "aemif");
> + clk_enable(aemif_clk);
> + clk_put(aemif_clk);
> +
> if (HAS_ATA) {
> if (HAS_NAND || HAS_NOR)
> pr_warning("WARNING: both IDE and Flash are "
> @@ -672,7 +679,7 @@ static __init void davinci_evm_irq_init(void)
> davinci_irq_init();
> }
>
> -MACHINE_START(DAVINCI_EVM, "DaVinci EVM")
> +MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
> /* Maintainer: MontaVista Software <[email protected]> */
> .phys_io = IO_PHYS,
> .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
> diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
> index cddd06b..93e3f02 100644
> --- a/arch/arm/mach-davinci/clock.c
> +++ b/arch/arm/mach-davinci/clock.c
> @@ -138,12 +138,19 @@ void clk_put(struct clk *clk)
> }
> EXPORT_SYMBOL(clk_put);
>
> +static unsigned psc_domain(struct clk *clk)
> +{
> + return (clk->flags & PSC_DSP)
> + ? DAVINCI_GPSC_DSPDOMAIN
> + : DAVINCI_GPSC_ARMDOMAIN;
> +}
> +
> static void __clk_enable(struct clk *clk)
> {
> if (clk->parent)
> __clk_enable(clk->parent);
> - if (clk->usecount++ == 0 && !(clk->flags & CLK_PLL))
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
> + if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
> + davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
> }
>
> static void __clk_disable(struct clk *clk)
> @@ -151,7 +158,7 @@ static void __clk_disable(struct clk *clk)
> if (WARN_ON(clk->usecount == 0))
> return;
> if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0);
> + davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
> if (clk->parent)
> __clk_disable(clk->parent);
> }
> @@ -230,7 +237,7 @@ int clk_register(struct clk *clk)
> if (clk->rate)
> return 0;
>
> - /* Otherwise, use parent rate and any divider */
> + /* Otherwise, default to parent rate */
> if (clk->parent)
> clk->rate = clk->parent->rate;
>
> @@ -256,17 +263,18 @@ EXPORT_SYMBOL(clk_unregister);
> static int __init clk_disable_unused(void)
> {
> struct clk *ck;
> - unsigned long flags;
>
> + spin_lock_irq(&clockfw_lock);
> list_for_each_entry(ck, &clocks, node) {
> if (ck->usecount > 0)
> continue;
> + if (!(ck->flags & CLK_PSC))
> + continue;
>
> printk(KERN_INFO "Clocks: disable unused %s\n", ck->name);
> - spin_lock_irqsave(&clockfw_lock, flags);
> - __clk_disable(ck);
> - spin_unlock_irqrestore(&clockfw_lock, flags);
> + davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
> }
> + spin_unlock_irq(&clockfw_lock);
>
> return 0;
> }
> @@ -278,17 +286,28 @@ static void clk_sysclk_recalc(struct clk *clk)
> u32 v, plldiv;
> struct pll_data *pll;
>
> - /* Immediate parent must be PLL */
> - if (WARN_ON(!clk->parent || !clk->parent->pll_data))
> + /* If this is the PLL base clock, no more calculations needed */
> + if (clk->pll_data)
> + return;
> +
> + if (WARN_ON(!clk->parent))
> return;
>
> - pll = clk->parent->pll_data;
> clk->rate = clk->parent->rate;
>
> - /* If bypass divider (BPDIV) use input reference clock */
> - if (clk->div_reg == BPDIV)
> + /* Otherwise, the parent must be a PLL */
> + if (WARN_ON(!clk->parent->pll_data))
> + return;
> +
> + pll = clk->parent->pll_data;
> +
> + /* If pre-PLL, source clock is before the multiplier and divider(s) */
> + if (clk->flags & PRE_PLL)
> clk->rate = pll->input_rate;
>
> + if (!clk->div_reg)
> + return;
> +
> v = __raw_readl(pll->base + clk->div_reg);
> if (v & PLLDIV_EN) {
> plldiv = (v & PLLDIV_RATIO_MASK) + 1;
> @@ -362,12 +381,16 @@ int __init davinci_clk_init(struct clk *clocks[])
> while ((clkp = clocks[i++])) {
> if (clkp->pll_data)
> clk_pll_init(clkp);
> - clk_register(clkp);
>
> /* Calculate rates for PLL-derived clocks */
> - if (clkp->div_reg)
> + else if (clkp->flags & CLK_PLL)
> clk_sysclk_recalc(clkp);
>
> + if (clkp->lpsc)
> + clkp->flags |= CLK_PSC;
> +
> + clk_register(clkp);
> +
> /* FIXME: remove equivalent special-cased code from
> * davinci_psc_init() once cpus list *all* clocks.
> */
> @@ -411,7 +434,10 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk
> *parent)
> struct clk *clk;
> unsigned i;
>
> - state = (parent->flags & CLK_PLL) ? "pll" : "psc";
> + if (parent->flags & CLK_PLL)
> + state = "pll";
> + else if (parent->flags & CLK_PSC)
> + state = "psc";
>
> /* <nest spaces> name <pad to end> */
> memset(buf, ' ', sizeof(buf) - 1);
> @@ -421,7 +447,7 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk
> *parent)
> min(i, (unsigned)(sizeof(buf) - 1 - nest)));
>
> seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
> - buf, parent->usecount, state, clk_get_rate(parent));
> + buf, parent->usecount, state ? : "", clk_get_rate(parent));
> /* REVISIT show device associations too */
>
> /* cost is now small, but not linear... */
> diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
> index 428edcf..c1191df 100644
> --- a/arch/arm/mach-davinci/clock.h
> +++ b/arch/arm/mach-davinci/clock.h
> @@ -71,7 +71,10 @@ struct clk {
>
> /* Clock flags */
> #define ALWAYS_ENABLED BIT(1)
> -#define CLK_PLL BIT(2)
> +#define CLK_PSC BIT(2)
> +#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
> +#define CLK_PLL BIT(4) /* PLL-derived clock */
> +#define PRE_PLL BIT(5) /* source is before PLL mult/div */
>
> int davinci_clk_associate(struct device *dev, const char *logical_clockname,
> const char *physical_clockname);
> diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
> index 42961ca..f934b54 100644
> --- a/arch/arm/mach-davinci/devices.c
> +++ b/arch/arm/mach-davinci/devices.c
> @@ -176,7 +176,7 @@ void __init davinci_setup_mmc(int module, struct
> davinci_mmc_config *config)
> davinci_cfg_reg(DM355_SD1_DATA3);
>
> pdev = &davinci_mmcsd1_device;
> - clockname = "MMCSDCLK1";
> + clockname = "mmcsd1";
> break;
> case 0:
> if (cpu_is_davinci_dm355()) {
> @@ -191,7 +191,7 @@ void __init davinci_setup_mmc(int module, struct
> davinci_mmc_config *config)
> davinci_cfg_reg(DM355_EVT26_MMC0_RX);
> }
> pdev = &davinci_mmcsd0_device;
> - clockname = cpu_is_davinci_dm355() ? "MMCSDCLK0" : "MMCSDCLK";
> + clockname = cpu_is_davinci_dm355() ? "mmcsd0" : "mmcsd";
> break;
> }
>
> diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
> index 8286753..51b24dd 100644
> --- a/arch/arm/mach-davinci/dm355.c
> +++ b/arch/arm/mach-davinci/dm355.c
> @@ -37,7 +37,6 @@ static struct clk ref_clk = {
> .name = "ref_clk",
> /* FIXME -- crystal rate is board-specific */
> .rate = DM355_REF_FREQ,
> - .flags = CLK_PLL,
> };
>
> static struct clk pll1_clk = {
> @@ -47,90 +46,120 @@ static struct clk pll1_clk = {
> .pll_data = &pll1_data,
> };
>
> -static struct clk pll2_clk = {
> - .name = "pll2",
> - .parent = &ref_clk,
> - .flags = CLK_PLL,
> - .pll_data = &pll2_data,
> -};
> -
> -static struct clk aux_clk = {
> - .name = "aux_clk",
> - .parent = &ref_clk,
> - .flags = CLK_PLL,
> +static struct clk pll1_aux_clk = {
> + .name = "pll1_aux_clk",
> + .parent = &pll1_clk,
> + .flags = CLK_PLL | PRE_PLL,
> };
>
> -static struct clk sysclk1_clk = {
> - .name = "SYSCLK1",
> +static struct clk pll1_sysclk1 = {
> + .name = "pll1_sysclk1",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV1,
> };
>
> -static struct clk sysclk2_clk = {
> - .name = "SYSCLK2",
> +static struct clk pll1_sysclk2 = {
> + .name = "pll1_sysclk2",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV2,
> };
>
> -static struct clk vpbe_clk = { /* a.k.a. PLL1.SYSCLK3 */
> - .name = "vpbe",
> +static struct clk pll1_sysclk3 = {
> + .name = "pll1_sysclk3",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV3,
> };
>
> -static struct clk vpss_clk = { /* a.k.a. PLL1.SYCLK4 */
> - .name = "vpss",
> +static struct clk pll1_sysclk4 = {
> + .name = "pll1_sysclk4",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV4,
> };
>
> +static struct clk pll1_sysclkbp = {
> + .name = "pll1_sysclkbp",
> + .parent = &pll1_clk,
> + .flags = CLK_PLL | PRE_PLL,
> + .div_reg = BPDIV
> +};
> +
> +static struct clk vpss_dac_clk = {
> + .name = "vpss_dac",
> + .parent = &pll1_sysclk3,
> + .lpsc = DM355_LPSC_VPSS_DAC,
> +};
> +
> +static struct clk vpss_master_clk = {
> + .name = "vpss_master",
> + .parent = &pll1_sysclk4,
> + .lpsc = DAVINCI_LPSC_VPSSMSTR,
> + .flags = CLK_PSC,
> +};
> +
> +static struct clk vpss_slave_clk = {
> + .name = "vpss_slave",
> + .parent = &pll1_sysclk4,
> + .lpsc = DAVINCI_LPSC_VPSSSLV,
> +};
> +
> +
> static struct clk clkout1_clk = {
> .name = "clkout1",
> - .parent = &aux_clk,
> - .flags = CLK_PLL,
> + .parent = &pll1_aux_clk,
> /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
> };
>
> -static struct clk clkout2_clk = { /* a.k.a. PLL1.SYSCLKBP */
> +static struct clk clkout2_clk = {
> .name = "clkout2",
> - .parent = &pll1_clk,
> + .parent = &pll1_sysclkbp,
> +};
> +
> +static struct clk pll2_clk = {
> + .name = "pll2",
> + .parent = &ref_clk,
> .flags = CLK_PLL,
> - .div_reg = BPDIV,
> + .pll_data = &pll2_data,
> };
>
> -static struct clk clkout3_clk = {
> - .name = "clkout3",
> +static struct clk pll2_sysclk1 = {
> + .name = "pll2_sysclk1",
> .parent = &pll2_clk,
> .flags = CLK_PLL,
> - .div_reg = BPDIV,
> + .div_reg = PLLDIV1,
> +};
> +
> +static struct clk pll2_sysclkbp = {
> + .name = "pll2_sysclkbp",
> + .parent = &pll2_clk,
> + .flags = CLK_PLL | PRE_PLL,
> + .div_reg = BPDIV
> +};
> +
> +static struct clk clkout3_clk = {
> + .name = "clkout3",
> + .parent = &pll2_sysclkbp,
> /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
> };
>
> static struct clk arm_clk = {
> - .name = "ARMCLK",
> - .parent = &sysclk1_clk,
> - .flags = ALWAYS_ENABLED | CLK_PLL,
> + .name = "arm_clk",
> + .parent = &pll1_sysclk1,
> + .lpsc = DAVINCI_LPSC_ARM,
> + .flags = ALWAYS_ENABLED,
> };
>
> /*
> - * NOT LISTED below, but turned on by PSC init:
> + * NOT LISTED below, and not touched by Linux
> * - in SyncReset state by default
> - * .lpsc = DAVINCI_LPSC_VPSSMSTR, .parent = &vpss_clk,
> - * .lpsc = DAVINCI_LPSC_VPSSSLV, .parent = &vpss_clk,
> * .lpsc = DAVINCI_LPSC_TPCC,
> * .lpsc = DAVINCI_LPSC_TPTC0,
> * .lpsc = DAVINCI_LPSC_TPTC1,
> - *
> - * NOT LISTED below, and not touched by Linux
> - * - in SyncReset state by default
> * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
> - * .lpsc = DM355_LPSC_RT0, .parent = &aux_clk,
> * .lpsc = DAVINCI_LPSC_MEMSTICK,
> - * .lpsc = 41, .parent = &vpss_clk, // VPSS DAC
> * - in Enabled state by default
> * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
> * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
> @@ -144,153 +173,165 @@ static struct clk arm_clk = {
>
> static struct clk mjcp_clk = {
> .name = "mjcp",
> - .parent = &sysclk1_clk,
> + .parent = &pll1_sysclk1,
> .lpsc = DAVINCI_LPSC_IMCOP,
> };
>
> static struct clk uart0_clk = {
> .name = "uart0",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_UART0,
> };
>
> static struct clk uart1_clk = {
> .name = "uart1",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_UART1,
> };
>
> static struct clk uart2_clk = {
> .name = "uart2",
> - .parent = &sysclk2_clk,
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_UART2,
> };
>
> static struct clk i2c_clk = {
> .name = "I2CCLK",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_I2C,
> };
>
> static struct clk asp0_clk = {
> - .name = "asp0_clk",
> - .parent = &sysclk2_clk,
> + .name = "asp0",
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_McBSP,
> };
>
> static struct clk asp1_clk = {
> - .name = "asp1_clk",
> - .parent = &sysclk2_clk,
> + .name = "asp1",
> + .parent = &pll1_sysclk2,
> .lpsc = DM355_LPSC_McBSP1,
> };
>
> static struct clk mmcsd0_clk = {
> - .name = "MMCSDCLK0",
> - .parent = &sysclk2_clk,
> + .name = "mmcsd0",
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_MMC_SD,
> };
>
> static struct clk mmcsd1_clk = {
> - .name = "MMCSDCLK1",
> - .parent = &sysclk2_clk,
> + .name = "mmcsd1",
> + .parent = &pll1_sysclk2,
> .lpsc = DM355_LPSC_MMC_SD1,
> };
>
> static struct clk spi0_clk = {
> - .name = "SPICLK",
> - .parent = &sysclk2_clk,
> + .name = "spi0",
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_SPI,
> };
>
> static struct clk spi1_clk = {
> - .name = "SPICLK1",
> - .parent = &sysclk2_clk,
> + .name = "spi1",
> + .parent = &pll1_sysclk2,
> .lpsc = DM355_LPSC_SPI1,
> };
>
> static struct clk spi2_clk = {
> - .name = "SPICLK2",
> - .parent = &sysclk2_clk,
> + .name = "spi2",
> + .parent = &pll1_sysclk2,
> .lpsc = DM355_LPSC_SPI2,
> };
> +
> static struct clk gpio_clk = {
> .name = "gpio",
> - .parent = &sysclk2_clk,
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_GPIO,
> };
>
> static struct clk aemif_clk = {
> - .name = "AEMIFCLK",
> - .parent = &sysclk2_clk,
> + .name = "aemif",
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_AEMIF,
> - .usecount = 1,
> };
>
> static struct clk pwm0_clk = {
> - .name = "PWM0_CLK",
> - .parent = &aux_clk,
> + .name = "pwm0",
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_PWM0,
> };
>
> static struct clk pwm1_clk = {
> - .name = "PWM1_CLK",
> - .parent = &aux_clk,
> + .name = "pwm1",
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_PWM1,
> };
>
> static struct clk pwm2_clk = {
> - .name = "PWM2_CLK",
> - .parent = &aux_clk,
> + .name = "pwm2",
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_PWM2,
> };
>
> static struct clk pwm3_clk = {
> - .name = "PWM3_CLK",
> - .parent = &aux_clk,
> + .name = "pwm3",
> + .parent = &pll1_aux_clk,
> .lpsc = DM355_LPSC_PWM3,
> };
>
> static struct clk timer0_clk = {
> .name = "timer0",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_TIMER0,
> };
>
> static struct clk timer1_clk = {
> .name = "timer1",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_TIMER1,
> };
>
> static struct clk timer2_clk = {
> .name = "timer2",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_TIMER2,
> };
>
> static struct clk timer3_clk = {
> .name = "timer3",
> - .parent = &aux_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DM355_LPSC_TIMER3,
> };
>
> +static struct clk rto_clk = {
> + .name = "rto",
> + .parent = &pll1_aux_clk,
> + .lpsc = DM355_LPSC_RTO,
> +};
> +
> static struct clk usb_clk = {
> - .name = "USBCLK",
> - .parent = &sysclk2_clk,
> + .name = "usb",
> + .parent = &pll1_sysclk2,
> .lpsc = DAVINCI_LPSC_USB,
> };
>
> static struct clk *dm355_clks[] __initdata = {
> &ref_clk,
> &pll1_clk,
> - &aux_clk,
> - &sysclk1_clk,
> - &sysclk2_clk,
> - &vpbe_clk,
> - &vpss_clk,
> + &pll1_sysclk1,
> + &pll1_sysclk2,
> + &pll1_sysclk3,
> + &pll1_sysclk4,
> + &pll1_aux_clk,
> + &pll1_sysclkbp,
> + &vpss_dac_clk,
> + &vpss_master_clk,
> + &vpss_slave_clk,
> &clkout1_clk,
> &clkout2_clk,
> &pll2_clk,
> + &pll2_sysclk1,
> + &pll2_sysclkbp,
> &clkout3_clk,
> &arm_clk,
> &mjcp_clk,
> @@ -315,6 +356,7 @@ static struct clk *dm355_clks[] __initdata = {
> &timer1_clk,
> &timer2_clk,
> &timer3_clk,
> + &rto_clk,
> &usb_clk,
> NULL,
> };
> diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
> index 680b1dd..c915a47 100644
> --- a/arch/arm/mach-davinci/dm644x.c
> +++ b/arch/arm/mach-davinci/dm644x.c
> @@ -34,7 +34,6 @@ static struct pll_data pll2_data = {
> static struct clk ref_clk = {
> .name = "ref_clk",
> .rate = DM644X_REF_FREQ,
> - .flags = CLK_PLL,
> };
>
> static struct clk pll1_clk = {
> @@ -44,154 +43,243 @@ static struct clk pll1_clk = {
> .flags = CLK_PLL,
> };
>
> -static struct clk pll2_clk = {
> - .name = "pll2",
> - .parent = &ref_clk,
> - .pll_data = &pll2_data,
> - .flags = CLK_PLL,
> -};
> -
> -static struct clk sysclk1_clk = {
> - .name = "SYSCLK1",
> +static struct clk pll1_sysclk1 = {
> + .name = "pll1_sysclk1",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV1,
> };
>
> -static struct clk sysclk2_clk = {
> - .name = "SYSCLK2",
> +static struct clk pll1_sysclk2 = {
> + .name = "pll1_sysclk2",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV2,
> };
>
> -static struct clk sysclk3_clk = {
> - .name = "SYSCLK3",
> +static struct clk pll1_sysclk3 = {
> + .name = "pll1_sysclk3",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV3,
> };
>
> -static struct clk sysclk5_clk = {
> - .name = "SYSCLK5",
> +static struct clk pll1_sysclk5 = {
> + .name = "pll1_sysclk5",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV5,
> };
>
> +static struct clk pll1_aux_clk = {
> + .name = "pll1_aux_clk",
> + .parent = &pll1_clk,
> + .flags = CLK_PLL | PRE_PLL,
> +};
> +
> +static struct clk pll1_sysclkbp = {
> + .name = "pll1_sysclkbp",
> + .parent = &pll1_clk,
> + .flags = CLK_PLL | PRE_PLL,
> + .div_reg = BPDIV
> +};
> +
> +static struct clk pll2_clk = {
> + .name = "pll2",
> + .parent = &ref_clk,
> + .pll_data = &pll2_data,
> + .flags = CLK_PLL,
> +};
> +
> +static struct clk pll2_sysclk1 = {
> + .name = "pll2_sysclk1",
> + .parent = &pll2_clk,
> + .flags = CLK_PLL,
> + .div_reg = PLLDIV1,
> +};
> +
> +static struct clk pll2_sysclk2 = {
> + .name = "pll2_sysclk2",
> + .parent = &pll2_clk,
> + .flags = CLK_PLL,
> + .div_reg = PLLDIV2,
> +};
> +
> +static struct clk pll2_sysclkbp = {
> + .name = "pll2_sysclkbp",
> + .parent = &pll2_clk,
> + .flags = CLK_PLL | PRE_PLL,
> + .div_reg = BPDIV
> +};
> +
> +static struct clk dsp_clk = {
> + .name = "dsp",
> + .parent = &pll1_sysclk1,
> + .lpsc = DAVINCI_LPSC_GEM,
> + .flags = PSC_DSP,
> + .usecount = 1, /* REVISIT how to disable? */
> +};
> +
> static struct clk arm_clk = {
> - .name = "ARMCLK",
> - .parent = &sysclk2_clk,
> - .lpsc = DAVINCI_LPSC_NONE,
> + .name = "arm",
> + .parent = &pll1_sysclk2,
> + .lpsc = DAVINCI_LPSC_ARM,
> .flags = ALWAYS_ENABLED,
> };
>
> +static struct clk vicp_clk = {
> + .name = "vicp",
> + .parent = &pll1_sysclk2,
> + .lpsc = DAVINCI_LPSC_IMCOP,
> + .flags = PSC_DSP,
> + .usecount = 1, /* REVISIT how to disable? */
> +};
> +
> +static struct clk vpss_master_clk = {
> + .name = "vpss_master",
> + .parent = &pll1_sysclk3,
> + .lpsc = DAVINCI_LPSC_VPSSMSTR,
> + .flags = CLK_PSC,
> +};
> +
> +static struct clk vpss_slave_clk = {
> + .name = "vpss_slave",
> + .parent = &pll1_sysclk3,
> + .lpsc = DAVINCI_LPSC_VPSSSLV,
> +};
> +
> static struct clk uart0_clk = {
> .name = "uart0",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_UART0,
> };
>
> static struct clk uart1_clk = {
> .name = "uart1",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_UART1,
> };
>
> static struct clk uart2_clk = {
> .name = "uart2",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_UART2,
> };
>
> static struct clk emac_clk = {
> .name = "EMACCLK",
> - .parent = &sysclk5_clk,
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
> };
>
> static struct clk i2c_clk = {
> .name = "I2CCLK",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_I2C,
> };
>
> static struct clk ide_clk = {
> .name = "IDECLK",
> - .parent = &sysclk5_clk,
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_ATA,
> };
>
> static struct clk asp_clk = {
> - .name = "asp0_clk",
> - .parent = &sysclk5_clk,
> + .name = "asp0",
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_McBSP,
> };
>
> static struct clk mmcsd_clk = {
> - .name = "MMCSDCLK",
> - .parent = &sysclk5_clk,
> + .name = "mmcsd",
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_MMC_SD,
> };
>
> static struct clk spi_clk = {
> - .name = "SPICLK",
> - .parent = &sysclk5_clk,
> + .name = "spi",
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_SPI,
> };
>
> static struct clk gpio_clk = {
> .name = "gpio",
> - .parent = &sysclk5_clk,
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_GPIO,
> };
>
> static struct clk usb_clk = {
> - .name = "USBCLK",
> - .parent = &sysclk5_clk,
> + .name = "usb",
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_USB,
> };
>
> static struct clk vlynq_clk = {
> - .name = "VLYNQCLK",
> - .parent = &sysclk5_clk,
> + .name = "vlynq",
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_VLYNQ,
> };
>
> static struct clk aemif_clk = {
> - .name = "AEMIFCLK",
> - .parent = &sysclk5_clk,
> + .name = "aemif",
> + .parent = &pll1_sysclk5,
> .lpsc = DAVINCI_LPSC_AEMIF,
> - .flags = ALWAYS_ENABLED,
> +};
> +
> +static struct clk pwm0_clk = {
> + .name = "pwm0",
> + .parent = &pll1_aux_clk,
> + .lpsc = DAVINCI_LPSC_PWM0,
> +};
> +
> +static struct clk pwm1_clk = {
> + .name = "pwm1",
> + .parent = &pll1_aux_clk,
> + .lpsc = DAVINCI_LPSC_PWM1,
> +};
> +
> +static struct clk pwm2_clk = {
> + .name = "pwm2",
> + .parent = &pll1_aux_clk,
> + .lpsc = DAVINCI_LPSC_PWM2,
> };
>
> static struct clk timer0_clk = {
> .name = "timer0",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_TIMER0,
> };
>
> static struct clk timer1_clk = {
> .name = "timer1",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_TIMER1,
> };
>
> static struct clk timer2_clk = {
> .name = "timer2",
> - .parent = &ref_clk,
> + .parent = &pll1_aux_clk,
> .lpsc = DAVINCI_LPSC_TIMER2,
> };
>
> static struct clk *dm644x_clks[] __initdata = {
> &ref_clk,
> &pll1_clk,
> + &pll1_sysclk1,
> + &pll1_sysclk2,
> + &pll1_sysclk3,
> + &pll1_sysclk5,
> + &pll1_aux_clk,
> + &pll1_sysclkbp,
> &pll2_clk,
> - &sysclk1_clk,
> - &sysclk2_clk,
> - &sysclk3_clk,
> - &sysclk5_clk,
> + &pll2_sysclk1,
> + &pll2_sysclk2,
> + &pll2_sysclkbp,
> + &dsp_clk,
> &arm_clk,
> + &vicp_clk,
> + &vpss_master_clk,
> + &vpss_slave_clk,
> &uart0_clk,
> &uart1_clk,
> &uart2_clk,
> @@ -205,6 +293,9 @@ static struct clk *dm644x_clks[] __initdata = {
> &usb_clk,
> &vlynq_clk,
> &aemif_clk,
> + &pwm0_clk,
> + &pwm1_clk,
> + &pwm2_clk,
> &timer0_clk,
> &timer1_clk,
> &timer2_clk,
> diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
> index 3f54872..ea97a72 100644
> --- a/arch/arm/mach-davinci/dm646x.c
> +++ b/arch/arm/mach-davinci/dm646x.c
> @@ -36,13 +36,11 @@ static struct pll_data pll2_data = {
> static struct clk ref_clk = {
> .name = "ref_clk",
> .rate = DM646X_REF_FREQ,
> - .flags = CLK_PLL,
> };
>
> -static struct clk aux_clk = {
> - .name = "aux_clk",
> +static struct clk aux_clkin = {
> + .name = "aux_clkin",
> .rate = DM646X_AUX_FREQ,
> - .flags = CLK_PLL,
> };
>
> static struct clk pll1_clk = {
> @@ -52,151 +50,190 @@ static struct clk pll1_clk = {
> .flags = CLK_PLL,
> };
>
> -static struct clk pll2_clk = {
> - .name = "pll2",
> - .parent = &ref_clk,
> - .pll_data = &pll2_data,
> - .flags = CLK_PLL,
> -};
> -
> -static struct clk sysclk1_clk = {
> - .name = "SYSCLK1",
> +static struct clk pll1_sysclk1 = {
> + .name = "pll1_sysclk1",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV1,
> };
>
> -static struct clk sysclk2_clk = {
> - .name = "SYSCLK2",
> +static struct clk pll1_sysclk2 = {
> + .name = "pll1_sysclk2",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV2,
> };
>
> -static struct clk sysclk3_clk = {
> - .name = "SYSCLK3",
> +static struct clk pll1_sysclk3 = {
> + .name = "pll1_sysclk3",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV3,
> };
>
> -static struct clk sysclk4_clk = {
> - .name = "SYSCLK4",
> +static struct clk pll1_sysclk4 = {
> + .name = "pll1_sysclk4",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV4,
> };
>
> -static struct clk sysclk5_clk = {
> - .name = "SYSCLK5",
> +static struct clk pll1_sysclk5 = {
> + .name = "pll1_sysclk5",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV5,
> };
>
> -static struct clk sysclk6_clk = {
> - .name = "SYSCLK6",
> +static struct clk pll1_sysclk6 = {
> + .name = "pll1_sysclk6",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV6,
> };
>
> -static struct clk sysclk8_clk = {
> - .name = "SYSCLK8",
> +static struct clk pll1_sysclk8 = {
> + .name = "pll1_sysclk8",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV8,
> };
>
> -static struct clk sysclk9_clk = {
> - .name = "SYSCLK9",
> +static struct clk pll1_sysclk9 = {
> + .name = "pll1_sysclk9",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV9,
> };
>
> -static struct clk sysclkbp_clk = {
> - .name = "SYSCLKBP",
> +static struct clk pll1_sysclkbp = {
> + .name = "pll1_sysclkbp",
> .parent = &pll1_clk,
> - .flags = CLK_PLL,
> + .flags = CLK_PLL | PRE_PLL,
> .div_reg = BPDIV,
> };
>
> +static struct clk pll1_aux_clk = {
> + .name = "pll1_aux_clk",
> + .parent = &pll1_clk,
> + .flags = CLK_PLL | PRE_PLL,
> +};
> +
> +static struct clk pll2_clk = {
> + .name = "pll2_clk",
> + .parent = &ref_clk,
> + .pll_data = &pll2_data,
> + .flags = CLK_PLL,
> +};
> +
> +static struct clk pll2_sysclk1 = {
> + .name = "pll2_sysclk1",
> + .parent = &pll2_clk,
> + .flags = CLK_PLL,
> + .div_reg = PLLDIV1,
> +};
> +
> +static struct clk dsp_clk = {
> + .name = "dsp",
> + .parent = &pll1_sysclk1,
> + .lpsc = DM646X_LPSC_C64X_CPU,
> + .flags = PSC_DSP,
> + .usecount = 1, /* REVISIT how to disable? */
> +};
> +
> static struct clk arm_clk = {
> - .name = "ARMCLK",
> - .parent = &sysclk2_clk,
> - .lpsc = DAVINCI_LPSC_NONE,
> + .name = "arm",
> + .parent = &pll1_sysclk2,
> + .lpsc = DM646X_LPSC_ARM,
> .flags = ALWAYS_ENABLED,
> };
>
> static struct clk uart0_clk = {
> .name = "uart0",
> - .parent = &aux_clk,
> + .parent = &aux_clkin,
> .lpsc = DM646X_LPSC_UART0,
> };
>
> static struct clk uart1_clk = {
> .name = "uart1",
> - .parent = &aux_clk,
> + .parent = &aux_clkin,
> .lpsc = DM646X_LPSC_UART1,
> };
>
> static struct clk uart2_clk = {
> .name = "uart2",
> - .parent = &aux_clk,
> + .parent = &aux_clkin,
> .lpsc = DM646X_LPSC_UART2,
> };
>
> static struct clk i2c_clk = {
> .name = "I2CCLK",
> - .parent = &sysclk3_clk,
> + .parent = &pll1_sysclk3,
> .lpsc = DM646X_LPSC_I2C,
> };
>
> static struct clk gpio_clk = {
> .name = "gpio",
> - .parent = &sysclk3_clk,
> + .parent = &pll1_sysclk3,
> .lpsc = DM646X_LPSC_GPIO,
> };
>
> static struct clk aemif_clk = {
> - .name = "AEMIFCLK",
> - .parent = &sysclk3_clk,
> + .name = "aemif",
> + .parent = &pll1_sysclk3,
> .lpsc = DM646X_LPSC_AEMIF,
> .flags = ALWAYS_ENABLED,
> };
>
> static struct clk emac_clk = {
> .name = "EMACCLK",
> - .parent = &sysclk3_clk,
> + .parent = &pll1_sysclk3,
> .lpsc = DM646X_LPSC_EMAC,
> };
>
> +static struct clk pwm0_clk = {
> + .name = "pwm0",
> + .parent = &pll1_sysclk3,
> + .lpsc = DM646X_LPSC_PWM0,
> + .usecount = 1, /* REVIST: disabling hangs system */
> +};
> +
> +static struct clk pwm1_clk = {
> + .name = "pwm1",
> + .parent = &pll1_sysclk3,
> + .lpsc = DM646X_LPSC_PWM1,
> + .usecount = 1, /* REVIST: disabling hangs system */
> +};
> +
> static struct clk timer0_clk = {
> .name = "timer0",
> - .parent = &sysclk3_clk,
> + .parent = &pll1_sysclk3,
> .lpsc = DM646X_LPSC_TIMER0,
> };
>
> static struct clk timer1_clk = {
> .name = "timer1",
> - .parent = &sysclk3_clk,
> + .parent = &pll1_sysclk3,
> .lpsc = DM646X_LPSC_TIMER1,
> };
>
> static struct clk *dm646x_clks[] __initdata = {
> &ref_clk,
> + &aux_clkin,
> &pll1_clk,
> - &sysclk1_clk,
> - &sysclk2_clk,
> - &sysclk3_clk,
> - &sysclk4_clk,
> - &sysclk5_clk,
> - &sysclk6_clk,
> - &sysclk8_clk,
> - &sysclk9_clk,
> - &sysclkbp_clk,
> + &pll1_sysclk1,
> + &pll1_sysclk2,
> + &pll1_sysclk3,
> + &pll1_sysclk4,
> + &pll1_sysclk5,
> + &pll1_sysclk6,
> + &pll1_sysclk8,
> + &pll1_sysclk9,
> + &pll1_sysclkbp,
> + &pll1_aux_clk,
> &pll2_clk,
> + &pll2_sysclk1,
> + &dsp_clk,
> &arm_clk,
> &uart0_clk,
> &uart1_clk,
> @@ -205,6 +242,8 @@ static struct clk *dm646x_clks[] __initdata = {
> &gpio_clk,
> &aemif_clk,
> &emac_clk,
> + &pwm0_clk,
> + &pwm1_clk,
> &timer0_clk,
> &timer1_clk,
> NULL,
> diff --git a/arch/arm/mach-davinci/include/mach/psc.h
> b/arch/arm/mach-davinci/include/mach/psc.h
> index 7edb362..11be379 100644
> --- a/arch/arm/mach-davinci/include/mach/psc.h
> +++ b/arch/arm/mach-davinci/include/mach/psc.h
> @@ -31,8 +31,6 @@
> #define DAVINCI_GPSC_ARMDOMAIN 0
> #define DAVINCI_GPSC_DSPDOMAIN 1
>
> -#define DAVINCI_LPSC_NONE 0xff
> -
> #define DAVINCI_LPSC_VPSSMSTR 0
> #define DAVINCI_LPSC_VPSSSLV 1
> #define DAVINCI_LPSC_TPCC 2
> @@ -40,8 +38,6 @@
> #define DAVINCI_LPSC_TPTC1 4
> #define DAVINCI_LPSC_EMAC 5
> #define DAVINCI_LPSC_EMAC_WRAPPER 6
> -#define DAVINCI_LPSC_MDIO 7
> -#define DAVINCI_LPSC_IEEE1394 8
> #define DAVINCI_LPSC_USB 9
> #define DAVINCI_LPSC_ATA 10
> #define DAVINCI_LPSC_VLYNQ 11
> @@ -49,7 +45,6 @@
> #define DAVINCI_LPSC_DDR_EMIF 13
> #define DAVINCI_LPSC_AEMIF 14
> #define DAVINCI_LPSC_MMC_SD 15
> -#define DAVINCI_LPSC_MEMSTICK 16
> #define DAVINCI_LPSC_McBSP 17
> #define DAVINCI_LPSC_I2C 18
> #define DAVINCI_LPSC_UART0 19
> @@ -82,11 +77,12 @@
> #define DM355_LPSC_PWM3 10
> #define DM355_LPSC_SPI2 11
> #define DM355_LPSC_RTO 12
> +#define DM355_LPSC_VPSS_DAC 41
>
> /*
> * LPSC Assignments
> */
> -#define DM646X_LPSC_RESERVED 0
> +#define DM646X_LPSC_ARM 0
> #define DM646X_LPSC_C64X_CPU 1
> #define DM646X_LPSC_HDVICP0 2
> #define DM646X_LPSC_HDVICP1 3
> diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
> index 1859a53..d2ed4fa 100644
> --- a/arch/arm/mach-davinci/psc.c
> +++ b/arch/arm/mach-davinci/psc.c
> @@ -124,9 +124,6 @@ void davinci_psc_config(unsigned int domain, unsigned int
> id, char enable)
> u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
> void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
>
> - if (id == DAVINCI_LPSC_NONE)
> - return;
> -
> mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
> if (enable)
> mdctl |= 0x00000003; /* Enable Module */
> @@ -187,17 +184,4 @@ void __init davinci_psc_init(void)
> pr_err("PSC: no PSC mux hooks for this CPU\n");
> davinci_psc_mux = nop_psc_mux;
> }
> -
> - if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) {
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN,
> - DAVINCI_LPSC_VPSSMSTR, 1);
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN,
> - DAVINCI_LPSC_VPSSSLV, 1);
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN,
> - DAVINCI_LPSC_TPCC, 1);
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN,
> - DAVINCI_LPSC_TPTC0, 1);
> - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN,
> - DAVINCI_LPSC_TPTC1, 1);
> - }
> }
> diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
> index 55e65b3..95094c9 100644
> --- a/arch/arm/mach-davinci/usb.c
> +++ b/arch/arm/mach-davinci/usb.c
> @@ -48,7 +48,7 @@ static struct musb_hdrc_platform_data usb_data = {
> #elif defined(CONFIG_USB_MUSB_HOST)
> .mode = MUSB_HOST,
> #endif
> - .clock = "USBCLK",
> + .clock = "usb",
> .config = &musb_config,
> };
>
> diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
> index 3fceb4c..984553a 100644
> --- a/drivers/mtd/nand/davinci_nand.c
> +++ b/drivers/mtd/nand/davinci_nand.c
> @@ -422,16 +422,17 @@ static int __init nand_davinci_probe(struct
> platform_device *pdev)
> }
> info->chip.ecc.mode = ecc_mode;
>
> - info->clk = clk_get(&pdev->dev, "AEMIFCLK");
> + info->clk = clk_get(&pdev->dev, "aemif");
> if (IS_ERR(info->clk)) {
> ret = PTR_ERR(info->clk);
> - dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret);
> + dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
> goto err_clk;
> }
>
> ret = clk_enable(info->clk);
> if (ret < 0) {
> - dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret);
> + dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
> + ret);
> goto err_clk_enable;
> }
>
> diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
> index 3d99184..3ef2a43 100644
> --- a/sound/soc/davinci/davinci-i2s.c
> +++ b/sound/soc/davinci/davinci-i2s.c
> @@ -401,7 +401,7 @@ static int davinci_i2s_probe(struct platform_device *pdev,
> struct resource *mem, *ioarea;
> struct evm_snd_platform_data *pdata;
> int ret;
> - static const char *clocks[] = { "asp0_clk", "asp1_clk", };
> + static const char *clocks[] = { "asp0", "asp1", };
>
> if (pdev->id < 0 || pdev->id > ARRAY_SIZE(clocks))
> return -EINVAL;
> --
> 1.6.1.2
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