From: Naresh Medisetty <[email protected]>

Move queue to tc mapping and queue priority mappings to
dm<soc>.c since the number of transfer controllers in
dm646x is four and number of transfer controllers in
dm644x/dm355 is two.

Signed-off-by: Naresh Medisetty <[email protected]>
---
 arch/arm/mach-davinci/dm355.c             |   19 ++++++++++++++++
 arch/arm/mach-davinci/dm644x.c            |   19 ++++++++++++++++
 arch/arm/mach-davinci/dm646x.c            |   34 ++++++++++++++++++++++++----
 arch/arm/mach-davinci/dma.c               |   22 +++++-------------
 arch/arm/mach-davinci/include/mach/edma.h |    6 +++++
 5 files changed, 79 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5f31649..05d4b3c 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -474,12 +474,31 @@ static const s8 dma_chan_dm355_no_event[] = {
        -1
 };
 
+static const int
+queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
+/* {event queue no, TC no} */
+       {0, 0},
+       {1, 1},
+       {-1, -1}
+};
+
+static const int
+queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
+       /* {event queue no, Priority} */
+       {0, 3},
+       {1, 7},
+       {-1, -1}
+};
+
+
 static struct edma_soc_info dm355_edma_info = {
        .n_channel      = 64,
        .n_region       = 4,
        .n_slot         = 128,
        .n_tc           = 2,
        .noevent        = dma_chan_dm355_no_event,
+       .queue_tc_mapping               = dm646x_queue_tc_mapping,
+       .queue_priority_mapping = dm646x_queue_priority_mapping,
 };
 
 static struct resource edma_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 03946fd..2c04b6a 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -373,12 +373,31 @@ static const s8 dma_chan_dm644x_no_event[] = {
        -1
 };
 
+static const int
+queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
+/* {event queue no, TC no} */
+       {0, 0},
+       {1, 1},
+       {-1, -1}
+};
+
+static const int
+queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
+       /* {event queue no, Priority} */
+       {0, 3},
+       {1, 7},
+       {-1, -1}
+};
+
+
 static struct edma_soc_info dm644x_edma_info = {
        .n_channel      = 64,
        .n_region       = 4,
        .n_slot         = 128,
        .n_tc           = 2,
        .noevent        = dma_chan_dm644x_no_event,
+       .queue_tc_mapping               = dm646x_queue_tc_mapping,
+       .queue_priority_mapping = dm646x_queue_priority_mapping,
 };
 
 static struct resource edma_resources[] = {
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index af040cf..0bdc397 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -287,12 +287,36 @@ static const s8 dma_chan_dm646x_no_event[] = {
        -1
 };
 
+/* dm646x specific */
+static const int
+dm646x_queue_tc_mapping[DM646X_EDMA_NUM_EVQUE + 1][2] = {
+/* {event queue no, TC no} */
+       {0, 0},
+       {1, 1},
+       {2, 2},
+       {3, 3},
+       {-1, -1}
+};
+
+static const int
+dm646x_queue_priority_mapping[DM646X_EDMA_NUM_EVQUE + 1][2] = {
+       /* {event queue no, Priority} */
+       {0, 4},
+       {1, 0},
+       {2, 5},
+       {3, 1},
+       {-1, -1}
+};
+
+
 static struct edma_soc_info dm646x_edma_info = {
-       .n_channel      = 64,
-       .n_region       = 6,    /* 0-1, 4-7 */
-       .n_slot         = 512,
-       .n_tc           = 4,
-       .noevent        = dma_chan_dm646x_no_event,
+       .n_channel                              = 64,
+       .n_region                               = 6,    /* 0-1, 4-7 */
+       .n_slot                                 = 512,
+       .n_tc                                   = 4,
+       .noevent                                = dma_chan_dm646x_no_event,
+       .queue_tc_mapping               = dm646x_queue_tc_mapping,
+       .queue_priority_mapping = dm646x_queue_priority_mapping,
 };
 
 static struct resource edma_resources[] = {
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index fc74ccc..575f13c 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -104,7 +104,7 @@
 
 #define EDMA_MAX_DMACH           64
 #define EDMA_MAX_PARAMENTRY     512
-#define EDMA_MAX_EVQUE            2    /* FIXME too small */
+
 
 
 /*****************************************************************************/
@@ -230,21 +230,6 @@ static const struct edmacc_param dummy_paramset = {
        .ccnt = 1,
 };
 
-static const int __initconst
-queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
-/* {event queue no, TC no} */
-       {0, 0},
-       {1, 1},
-       {-1, -1}
-};
-
-static const int __initconst
-queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
-       /* {event queue no, Priority} */
-       {0, 3},
-       {1, 7},
-       {-1, -1}
-};
 
 /*****************************************************************************/
 
@@ -995,6 +980,8 @@ static int __init edma_probe(struct platform_device *pdev)
        int                     i;
        int                     status;
        const s8                *noevent;
+       const int (*queue_tc_mapping)[2];
+       const int (*queue_priority_mapping)[2];
        int                     irq = 0, err_irq = 0;
        struct resource         *r;
        resource_size_t         len;
@@ -1073,6 +1060,9 @@ static int __init edma_probe(struct platform_device *pdev)
         */
        for (i = 0; i < num_channels; i++)
                map_dmach_queue(i, EVENTQ_1);
+       queue_tc_mapping = info->queue_tc_mapping;
+       queue_priority_mapping = info->queue_priority_mapping;
+
 
        /* Event queue to TC mapping */
        for (i = 0; queue_tc_mapping[i][0] != -1; i++)
diff --git a/arch/arm/mach-davinci/include/mach/edma.h 
b/arch/arm/mach-davinci/include/mach/edma.h
index c16e383..8a80a9e 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -75,6 +75,10 @@ struct edmacc_param {
 #define TCERRINT0_INTERRUPT   18
 #define TCERRINT1_INTERRUPT   19
 
+#define EDMA_MAX_EVQUE            2    /* FIXME too small */
+/* dm646x specific */
+#define DM646X_EDMA_NUM_EVQUE            4
+
 /* fields in edmacc_param.opt */
 #define SAM            BIT(0)
 #define DAM            BIT(1)
@@ -223,6 +227,8 @@ struct edma_soc_info {
 
        /* list of channels with no even trigger; terminated by "-1" */
        const s8        *noevent;
+       const int (*queue_tc_mapping)[2];
+       const int (*queue_priority_mapping)[2];
 };
 
 #endif
-- 
1.5.6

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