Sudhakar Rajashekhara wrote:
From: David Griego <[email protected]>
Adds edma_clear_event API support to EDMA.
There has been a change to the MMC interface on TI's DA830/OMAP-L137
architecture that requires setting the DMATRIG bit to trigger
the first read data transfer when doing a read operation using
the CPU, but it has the unintended consequence causing a DMA
event. Because of this, the next DMA read from the MMC/SD will
fail with an Event Miss. This API will be used to clear the ER.
Signed-off-by: David Griego <[email protected]>
Signed-off-by: Sergei Shtylyov <[email protected]>
Signed-off-by: Sudhakar Rajashekhara <[email protected]>
---
arch/arm/mach-davinci/dma.c | 18 ++++++++++++++++++
arch/arm/mach-davinci/include/mach/edma.h | 1 +
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index fc74ccc..9427c80 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -95,6 +95,8 @@
#define EDMA_CCSTAT 0x0640
#define EDMA_M 0x1000 /* global channel registers */
+#define EDMA_ECR 0x1008
+#define EDMA_ECRH 0x100C
#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
#define EDMA_PARM 0x4000 /* 128 param entries */
@@ -987,6 +989,22 @@ void edma_clean_channel(unsigned channel)
}
EXPORT_SYMBOL(edma_clean_channel);
+/*
+ * edma_clear_event - clear an outstanding event on the DMA channel
+ * Arguments:
+ * channel - channel number
+ */
+void edma_clear_event(unsigned channel)
+{
+ if (channel >= num_channels)
+ return;
+ if (channel < 32)
+ edma_write(EDMA_ECR, 1 << channel);
+ else
+ edma_write(EDMA_ECRH, 1 << (channel - 32));
+}
+EXPORT_SYMBOL(edma_clear_event);
+
/*-----------------------------------------------------------------------*/
This seems to me like a work-around for shutting down a DMA channel
without waiting for any pending events to finish first. Wouldn't not
clearing ECR in edma_stop and writing a null param set in edma_free_slot
handle this correctly? The behavior seems very similar to the issue I
encountered with the ASoC pcm code and EDMA and that was my solution.
Along with serialization of the pcm interrupt callback and pcm trigger.
This goes back to clearing the ECR register on start basically, be it
from the peripheral driver.
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