From: Naresh Medisetty <[email protected]> EDMA in DM355 and DM644x has two transfer controllers while DM646x has four transfer controllers. Moving the queue to tc mapping and queue priority mapping to dm<soc>.c will be helpful to probe these mappings from platform device so that the machine_is_* testing will be avoided.
Signed-off-by: Naresh Medisetty <[email protected]> --- arch/arm/mach-davinci/dm355.c | 30 ++++++++++++++++++++---- arch/arm/mach-davinci/dm644x.c | 30 ++++++++++++++++++++---- arch/arm/mach-davinci/dm646x.c | 36 ++++++++++++++++++++++++----- arch/arm/mach-davinci/dma.c | 22 +++-------------- arch/arm/mach-davinci/include/mach/edma.h | 6 +++++ 5 files changed, 90 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 5f31649..ee92c10 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -474,12 +474,32 @@ static const s8 dma_chan_dm355_no_event[] = { -1 }; +static const s8 +queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { +/* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const s8 +queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + + static struct edma_soc_info dm355_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm355_no_event, + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .noevent = dma_chan_dm355_no_event, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, + }; static struct resource edma_resources[] = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 6a08568..d1f5790 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -396,13 +396,33 @@ static const s8 dma_chan_dm644x_no_event[] = { 63, -1 }; +static const s8 +queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { +/* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const s8 +queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + + static struct edma_soc_info dm644x_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm644x_no_event, + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .noevent = dma_chan_dm644x_no_event, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, + }; static struct resource edma_resources[] = { diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index b302f12..5ef83a4 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -362,15 +362,39 @@ static const s8 dma_chan_dm646x_no_event[] = { 56, -1 }; +/* Four Transfer Controllers on DM646x */ +static const s8 +dm646x_queue_tc_mapping[DM646X_EDMA_NUM_EVQUE + 1][2] = { +/* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1} +}; -static struct edma_soc_info dm646x_edma_info = { - .n_channel = 64, - .n_region = 6, /* 0-1, 4-7 */ - .n_slot = 512, - .n_tc = 4, - .noevent = dma_chan_dm646x_no_event, +static const s8 +dm646x_queue_priority_mapping[DM646X_EDMA_NUM_EVQUE + 1][2] = { + /* {event queue no, Priority} */ + {0, 4}, + {1, 0}, + {2, 5}, + {3, 1}, + {-1, -1} }; + + +static struct edma_soc_info dm646x_edma_info = { + .n_channel = 64, + .n_region = 6, /* 0-1, 4-7 */ + .n_slot = 512, + .n_tc = 4, + .noevent = dma_chan_dm646x_no_event, + .queue_tc_mapping = dm646x_queue_tc_mapping, + .queue_priority_mapping = dm646x_queue_priority_mapping, + +}; static struct resource edma_resources[] = { { .name = "edma_cc", diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 9427c80..37a506f 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -106,8 +106,6 @@ #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_MAX_EVQUE 2 /* FIXME too small */ - /*****************************************************************************/ @@ -232,22 +230,6 @@ static const struct edmacc_param dummy_paramset = { .ccnt = 1, }; -static const int __initconst -queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { -/* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {-1, -1} -}; - -static const int __initconst -queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1} -}; - /*****************************************************************************/ static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no) @@ -1013,6 +995,8 @@ static int __init edma_probe(struct platform_device *pdev) int i; int status; const s8 *noevent; + const s8 (*queue_tc_mapping)[2]; + const s8 (*queue_priority_mapping)[2]; int irq = 0, err_irq = 0; struct resource *r; resource_size_t len; @@ -1091,6 +1075,8 @@ static int __init edma_probe(struct platform_device *pdev) */ for (i = 0; i < num_channels; i++) map_dmach_queue(i, EVENTQ_1); + queue_tc_mapping = info->queue_tc_mapping; + queue_priority_mapping = info->queue_priority_mapping; /* Event queue to TC mapping */ for (i = 0; queue_tc_mapping[i][0] != -1; i++) diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index b467358..8c50544 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -74,6 +74,9 @@ struct edmacc_param { #define CCERRINT_INTERRUPT 17 #define TCERRINT0_INTERRUPT 18 #define TCERRINT1_INTERRUPT 19 +#define EDMA_MAX_EVQUE 2 /* FIXME too small */ +/* dm646x specific */ +#define DM646X_EDMA_NUM_EVQUE 4 /* fields in edmacc_param.opt */ #define SAM BIT(0) @@ -224,6 +227,9 @@ struct edma_soc_info { /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; + const s8 (*queue_tc_mapping)[2]; + const s8 (*queue_priority_mapping)[2]; + }; #endif -- 1.5.6 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
