On Thursday 07 May 2009, vimal singh wrote: > >> How about leaving bytes '4' and '5' for bad block marker, to support 16-bit > >> NAND parts too. > > > > This 4-bit ECC engine only works for 8-bit wide parts ... > > or are you suggesting that in case TI re-engineers that > > engine in the future? > > I am omap guy and was not aware of that. In omap HW BCH > ECC (4- or 8- bit correction)can work both kind of memories.
I'm somewhat more of an OMAP guy too -- just got sucked in to trying to get a dm355 board to run off NAND in mainline-bound code, and you can see where that landed me! Last I looked at the OMAP2/OMAP3 NAND controller driver, it didn't yet support most fancy hardware features, like ECC using more than one bit or the prefetch/postwrite logic. One nice feature of that OMAP2/OMAP3 controller, beyond the support for 8 bit ECC, is that it buffers the ECC syndrome data so that it doesn't need NAND_ECC_HW_OOB_FIRST logic to prevent trashing the manufacturer OOB markers. The limit of max 4K pages seems like not a big worry for now. - Dave _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
