On Tuesday 12 May 2009, Vijay Soni wrote: > Does anyone know what code changes would be required to > have multiple nand flash support on dm355 based hardware.
What happens when you try the obvious simple thing: one davinci_nand platform device for each chipselect? My question has been about handling the AEMIF control bank. That's been a bit messy all along ... it's not naturally part of any single chip. > The different nand flash will have different nand base > addresses (due to external chip select multiplexer) and > all need to be seen by kernel. Further, we have three nand > flash, of which the boot nand is same as in evm(2k page > size) ... and has two chipselects, gated by some address bit; appears to Linux like two separate chips in one bank. > but the other two are 4k page size nand flashes. _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
