On Thu, 2009-05-14 at 10:51 +0800, Liu Yebo wrote: > Hi, > > I've been doing some testing with SD card writes on the our dm355 > board.That looks that the performance is dismal, that is pretty poor. > i was getting speeds of around 2-3MB/s for write. > > Now i have enable high speed SD support.Note that on the dm355 cards > won't clock over 27 MHZ because the functional clock is at 108 MHZ,and > the divider does not allow a divide-by-three. The MMC/SD contrcoller > specs say that it only supports > up to 100 MHZ for a functional clock.
I was looking at SD performance on DA830/OMAP-l137. The functional clock for DA830 is at 150MHz, and the throughput is even lower. I don't know if there is a correlation. I sent an inquiry e-mail to TI on this very topic a couple of days ago. According to TI, the design with higher functional clock passed hardware simulation, but they are not sure if the higher clock frequency affects performance. TI has not got back to me on the performance question yet. As for kernel debugging, I noticed that the kernel spends most of the time waiting for EDATDNE (data done) interrupt. As a test, I enabled the ETRNDNE (transfer complete). I found that most of the delays are between ETRNDNE and EDATNE. The only thing that is suppose to happen between these two interrupts is CRC calculation and validation between the MMC/SD controller the SD device. This is done in hardware. At this point, I'm out of debugging ideas. I'm waiting for reply from TI. Hopefully, their emails can provide new ideas and directions. Regards, Steve _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
