The changes mainly target two areas: 1) Provide clock structure, setting up PCI
PINMUX and perform board specific fix-ups for PCI Host core to begin
configuration/enumeraion and 2) Provide PCI IO access through in/outx() and
ioread/iowritex().
The arm-kernel configuration is updated to support PCI Bus for DM646x builds.
In addition, I/O mapping macros are moved inside hardware.h to avoid the need
for inclusion of io.h in assembly files which results in assembler errors for
PCI I/O functions, as well as serial.h, which results in unresolved symbols for
PCI I/O functions (in uncompress code).
Signed-off-by: Hemant Pedanekar <hema...@ti.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-davinci/Kconfig | 1 +
arch/arm/mach-davinci/Makefile | 6 +
arch/arm/mach-davinci/board-dm646x-evm.c | 82 ++++++++
arch/arm/mach-davinci/dm646x.c | 22 ++-
arch/arm/mach-davinci/include/mach/dm646x.h | 33 +++-
arch/arm/mach-davinci/include/mach/entry-macro.S | 2 +-
arch/arm/mach-davinci/include/mach/hardware.h | 21 ++
arch/arm/mach-davinci/include/mach/io.h | 237 ++++++++++++++++++++--
arch/arm/mach-davinci/include/mach/mux.h | 10 +-
arch/arm/mach-davinci/include/mach/serial.h | 2 +-
arch/arm/mach-davinci/include/mach/vmalloc.h | 2 +-
12 files changed, 390 insertions(+), 30 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf935b0..3324c02 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -776,7 +776,7 @@ config ISA_DMA_API
bool
config PCI
- bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB ||
ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+ bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB ||
ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_DAVINCI_DM646x
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index c460615..2ce0ffd 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -17,6 +17,7 @@ config ARCH_DAVINCI_DM644x
config ARCH_DAVINCI_DM646x
bool "DaVinci 646x based system"
select AINTC
+ select DAVINCI_MUX if PCI
config ARCH_DAVINCI_DM355
bool "DaVinci 355 based system"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
old mode 100644
new mode 100755
index 6da7b63..7323c83
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -9,12 +9,18 @@ obj-y := time.o clock.o serial.o io.o
psc.o \
sram.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
+obj-$(CONFIG_PCI) += pci-generic.o
# Chip specific
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o
+# PCI - Chip specific
+ifeq ($(CONFIG_PCI), y)
+obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pci-dm6467.o
+endif
+
obj-$(CONFIG_AINTC) += irq.o
obj-$(CONFIG_CP_INTC) += cp_intc.o
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c
b/arch/arm/mach-davinci/board-dm646x-evm.c
old mode 100644
new mode 100755
index a55f45c..8423d15
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -37,11 +37,13 @@
#include <asm/mach/flash.h>
#include <mach/dm646x.h>
#include <mach/common.h>
+#include <mach/mux.h>
#include <mach/psc.h>
#include <mach/serial.h>
#include <mach/i2c.h>
#include <mach/mmc.h>
#include <mach/common.h>
+#include <mach/emac.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
@@ -65,6 +67,54 @@ static struct gpio_led evm_leds[] = {
{ .name = "DS4", .active_low = 1, },
};
+/* Setup DM6467 for PCI mode. In case of default EVM, the CPLD along with FET
+ * switches takes care of switching to PCI Boot mode when the EVM is put in
+ * the PCI slot and this funtion needs to do nothing. While in case when the
+ * CPLD code/ Hardware is reworked (not to do autoswitch), the code below
+ * handles mux configurations to switch to PCI (Host) mode and takes care of
+ * driving RST# over PCI Bus.
+ */
+static void dm646xevm_pci_setup(void)
+{
+ void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+
+ /* Skip this if PCIEN is already set in PINMUX0 */
+ if (!((__raw_readl(base + PINMUX0)) & (1<<2))) {
+ /* Power up the I/O cells for PCI interface */
+ __raw_writel(__raw_readl(base + DM64XX_VDD3P3V_PWDN)
+ & ~(3<<16), base + DM64XX_VDD3P3V_PWDN);
+
+ davinci_cfg_reg(DM646X_HPI32EN);
+
+ /* Drive GPIO[13] High to avoid reset when PCI is
+ * enabled
+ */
+ if (gpio_request(13, "RST#") != 0) {
+ pr_err("Request for GPIO13 failed.\n");
+ return;
+ }
+
+ gpio_direction_output(13, 1);
+
+ /* Ensure AUDCK1 is disabled to control GPIO[2] */
+ davinci_cfg_reg(DM646X_AUDCK1_DISABLE);
+
+ davinci_cfg_reg(DM646X_PCIEN);
+
+ /* Drive GPIO[2] high to take the PCI bus out of reset
+ * (drive RST#) and select B2 of the FET mux on EVM to
+ * deselect NAND and switch to PCI Bus
+ */
+ if (gpio_request(2, "PCIRST#") != 0) {
+ pr_err("Request for GPIO2 failed.\n");
+ return;
+ }
+ gpio_direction_output(2, 1);
+ } else {
+ pr_info("PCI_EN is already asserted.\n");
+ }
+}
+
static __initconst struct gpio_led_platform_data evm_led_data = {
.num_leds = ARRAY_SIZE(evm_leds),
.leds = evm_leds,
@@ -233,10 +283,42 @@ static void __init davinci_map_io(void)
dm646x_init();
}
+#if defined(CONFIG_PCI)
+#define HAS_PCI 1
+#else
+#define HAS_PCI 0
+#endif
+
+#if defined(CONFIG_IDE) || \
+ defined(CONFIG_IDE_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+#if defined(CONFIG_MTD_NAND_DAVINCI) || \
+ defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
+#define HAS_NAND 1
+#else
+#define HAS_NAND 0
+#endif
+
static __init void evm_init(void)
{
struct davinci_soc_info *soc_info = davinci_get_soc_info();
+ if (HAS_PCI) {
+ if (HAS_ATA)
+ pr_warning("WARNING: both PCI and IDE are "
+ "enabled, but they share some pins.\n"
+ "\tDisable PCI for IDE support.\n");
+ else if (HAS_NAND)
+ pr_warning("WARNING: both PCI and Flash are "
+ "enabled, but they share AEMIF pins.\n"
+ "\tDisable PCI for NAND/NOR support.\n");
+ dm646xevm_pci_setup();
+ }
+
evm_init_i2c();
davinci_serial_init(&uart_config);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
old mode 100644
new mode 100755
index 3cd09c1..d53a2d2
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -26,6 +26,7 @@
#include <mach/time.h>
#include <mach/gpio.h>
#include <mach/serial.h>
+#include <mach/emac.h>
#include <mach/common.h>
#include "clock.h"
@@ -251,6 +252,13 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
+static struct clk pci_clk = {
+ .name = "pci",
+ .parent = &pll1_sysclk2,
+ .lpsc = DM646X_LPSC_PCI,
+ .flags = CLK_PSC,
+};
+
struct davinci_clk dm646x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "aux", &aux_clkin),
@@ -280,6 +288,7 @@ struct davinci_clk dm646x_clks[] = {
CLK(NULL, "pwm1", &pwm1_clk),
CLK(NULL, "timer0", &timer0_clk),
CLK(NULL, "timer1", &timer1_clk),
+ CLK(NULL, "pci", &pci_clk),
CLK("watchdog", NULL, &timer2_clk),
CLK(NULL, "vpif0", &vpif0_clk),
CLK(NULL, "vpif1", &vpif1_clk),
@@ -333,9 +342,6 @@ static struct platform_device dm646x_emac_device = {
.resource = dm646x_emac_resources,
};
-#define PINMUX0 0x00
-#define PINMUX1 0x04
-
/*
* Device specific mux setup
*
@@ -344,11 +350,15 @@ static struct platform_device dm646x_emac_device = {
*/
static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
+MUX_CFG(DM646X, ATAEN, 0, 0, 7, 1, true)
+
+MUX_CFG(DM646X, PCIEN, 0, 0, 7, 4, true)
+
+MUX_CFG(DM646X, HPI32EN, 0, 0, 7, 2, true)
-MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
+MUX_CFG(DM646X, AUDCK1_DISABLE, 0, 29, 1, 0, false)
-MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
+MUX_CFG(DM646X, AUDCK0_DISABLE, 0, 28, 1, 0, false)
MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h
b/arch/arm/mach-davinci/include/mach/dm646x.h
old mode 100644
new mode 100755
index 7afc613..2503ad3
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -11,10 +11,6 @@
#ifndef __ASM_ARCH_DM646X_H
#define __ASM_ARCH_DM646X_H
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <mach/emac.h>
-
#define DM646X_EMAC_BASE (0x01C80000)
#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
@@ -22,6 +18,35 @@
#define DM646X_EMAC_MDIO_OFFSET (0x4000)
#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
+/* Checked during PCI Enumeration of Bridges */
+#define pcibios_assign_all_busses() 1
+
+/*
+ * PCI Resource allocation
+ */
+
+/* PCI IO window.
+ * This could be set anywhere in the 4G space by adjusting PCIBIOS_MIN_IO and
+ * PCIBIOS_MAX_IO, which, in turn are used by in/out macros to distinguish
+ * between PCU IO and normal MMIO.
+ * Currently using 32M reserved window from DM6467 memory map.
+ */
+#define PCIBIOS_MIN_IO 0x4A000000
+#define PCIBIOS_MAX_IO 0x4BFFFFFF
+
+/* PCI Memory window base */
+#define PCIBIOS_MIN_MEM 0x30000000
+
+#define DAVINCI_DM646X_PCI_CTL_BASE (0x01C1A000)
+
+/* System module registers */
+#define PINMUX0 0x00
+#define PINMUX1 0x04
+#define BOOTCFG 0x14
+
+#ifndef __ASSEMBLY__
+#include <linux/init.h>
void __init dm646x_init(void);
+#endif
#endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S
b/arch/arm/mach-davinci/include/mach/entry-macro.S
old mode 100644
new mode 100755
index fbdebc7..cf098a8
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -8,7 +8,7 @@
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
-#include <mach/io.h>
+#include <mach/hardware.h>
#include <mach/irqs.h>
.macro disable_fiq
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h
b/arch/arm/mach-davinci/include/mach/hardware.h
old mode 100644
new mode 100755
index 48c7793..fb78064
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -11,6 +11,10 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
+#if defined(CONFIG_ARCH_DAVINCI_DM646x)
+#include <mach/dm646x.h>
+#endif
+
/*
* Before you add anything to ths file:
*
@@ -24,4 +28,21 @@
/* System control register offsets */
#define DM64XX_VDD3P3V_PWDN 0x48
+/*
+ * I/O mapping
+ */
+#define IO_PHYS 0x01c00000
+#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
+#define IO_SIZE 0x00400000
+#define IO_VIRT (IO_PHYS + IO_OFFSET)
+#define io_v2p(va) ((va) - IO_OFFSET)
+#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
+#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x) x
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h
b/arch/arm/mach-davinci/include/mach/io.h
old mode 100644
new mode 100755
index 2479785..19a74c9
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -11,29 +11,238 @@
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
+#include <mach/hardware.h>
-/*
- * ----------------------------------------------------------------------------
- * I/O mapping
- * ----------------------------------------------------------------------------
- */
-#define IO_PHYS 0x01c00000
-#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
-#define IO_SIZE 0x00400000
-#define IO_VIRT (IO_PHYS + IO_OFFSET)
-#define io_v2p(va) ((va) - IO_OFFSET)
-#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
+#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
-#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
-#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
+#if defined(CONFIG_PCI)
+/*
+ * Here we provide DMSoC to PCI I/O space access as PCI I/O is performed
+ * indirectly by accessing PCI IO Register.
+ *
+ * We will still use the default I/O (memory mapped for ARM) for any access
+ * which is outside the allotted PCI I/O window. Note: In this case we
replicate
+ * the default inx/outx behavior as found in include/asm-arm/io.h (except of
+ * course, addition of sequence point, which is not needed in our case).
+ */
+#define CFG_PCIM_IO_START (PCIBIOS_MIN_IO)
+#define CFG_PCIM_IO_END 0x4BFFFFFF
+
+#define outb(v, p) _davinci_outb(v, p)
+#define outw(v, p) _davinci_outw(v, p)
+#define outl(v, p) _davinci_outl(v, p)
+
+/* REVISIT: Using incremental access currently, need to check h/w support */
+#define outsb(p, d, l) _davinci_outsb(p, d, l)
+#define outsw(p, d, l) _davinci_outsw(p, d, l)
+#define outsl(p, d, l) _davinci_outsl(p, d, l)
+
+#define inb(p) _davinci_inb(p)
+#define inw(p) _davinci_inw(p)
+#define inl(p) _davinci_inl(p)
+
+/* REVISIT: Using incremental access currently, need to check h/w support */
+#define insb(p, d, l) _davinci_insb(p, d, l)
+#define insw(p, d, l) _davinci_insw(p, d, l)
+#define insl(p, d, l) _davinci_insl(p, d, l)
+
+/* Check if the supplied (physical) address falls withing the PCI IO window */
+#define IS_PCI_IO(p) (((p) >= PCIBIOS_MIN_IO) \
+ && ((p) <= PCIBIOS_MAX_IO))
+
+/*
+ * I/O Functions
+ */
+#define PCI_ACCESS_TYPE_CFG 0
+#define PCI_ACCESS_TYPE_IO 1
+extern int ti_pci_io_write(u32 addr, int size, u32 value);
+extern int ti_pci_io_read(u32 addr, int size, u32 *value);
+
+static inline void _davinci_outb(u8 value, u32 addr)
+{
+ if (IS_PCI_IO(addr))
+ ti_pci_io_write(addr, 1, (u32)value);
+ else
+ __raw_writeb(value, __typesafe_io(addr));
+}
+
+static inline void _davinci_outsb(u32 addr, const void *data, u32 blen)
+{
+ while (blen--)
+ _davinci_outb(*(const u8 *)data++, (u32)((u8 *)addr++));
+}
+
+static inline void _davinci_outw(u16 value, u32 addr)
+{
+ if (IS_PCI_IO(addr))
+ ti_pci_io_write(addr, 2, (u32)value);
+ else
+ __raw_writew(cpu_to_le16(value), __typesafe_io(addr));
+}
+
+static inline void _davinci_outsw(u32 addr, const void *data, u32 wlen)
+{
+ while (wlen--)
+ _davinci_outw(*(const u16 *)data++, (u32)((u16 *)addr++));
+}
+
+static inline void _davinci_outl(u32 value, u32 addr)
+{
+ if (IS_PCI_IO(addr))
+ ti_pci_io_write(addr, 4, (u32)value);
+ else
+ __raw_writel(cpu_to_le32(value), __typesafe_io(addr));
+}
+
+static inline void _davinci_outsl(u32 addr, const void *data, u32 llen)
+{
+ while (llen--)
+ _davinci_outl(*(const u32 *)data++, (u32)((u32 *)addr++));
+}
+
+static inline u8 _davinci_inb(u32 addr)
+{
+ if (IS_PCI_IO(addr)) {
+ u32 value;
+ ti_pci_io_read(addr, 1, &value);
+ return (u8)value;
+ } else
+ return __raw_readb(__typesafe_io(addr));
+}
+
+static inline void _davinci_insb(u32 addr, void *data, u32 blen)
+{
+ while (blen--)
+ *(u8 *)data++ = _davinci_inb((u32)((u8 *)addr++));
+}
+
+static inline u16 _davinci_inw(u32 addr)
+{
+ if (IS_PCI_IO(addr)) {
+ u32 value;
+ ti_pci_io_read(addr, 2, &value);
+ return (u16)value;
+ } else
+ return le16_to_cpu(__raw_readw(__typesafe_io(addr)));
+}
+
+static inline void _davinci_insw(u32 addr, void *data, u32 wlen)
+{
+ while (wlen--)
+ *(u16 *)data++ = _davinci_inw((u32)((u16 *)addr++));
+}
+
+static inline u32 _davinci_inl(u32 addr)
+{
+ if (IS_PCI_IO(addr)) {
+ u32 value;
+ ti_pci_io_read(addr, 4, &value);
+ return value;
+ } else
+ return le32_to_cpu(__raw_readl(__typesafe_io(addr)));
+}
+
+static inline void _davinci_insl(u32 addr, void *data, u32 llen)
+{
+ while (llen--)
+ *(u32 *)data++ = _davinci_inl((u32)((u32 *)addr++));
+}
+
+static inline unsigned int _davinci_ioread8(void __iomem *port)
+{
+ return (unsigned int)_davinci_inb((unsigned long __force)port);
+}
+
+static inline void _davinci_ioread8_rep(void __iomem *port, void *dst,
+ unsigned long count)
+{
+ _davinci_insb((unsigned long __force)port, dst, count);
+}
+
+static inline unsigned int _davinci_ioread16(void __iomem *port)
+{
+ return (unsigned int)_davinci_inw((unsigned long __force)port);
+}
+
+static inline void _davinci_ioread16_rep(void __iomem *port, void *dst,
+ unsigned long count)
+{
+ _davinci_insw((unsigned long __force)port, dst, count);
+}
+
+static inline unsigned int _davinci_ioread32(void __iomem *port)
+{
+ return (unsigned int)_davinci_inl((unsigned long __force)port);
+}
+
+static inline void _davinci_ioread32_rep(void __iomem *port, void *dst,
+ unsigned long count)
+{
+ _davinci_insl((unsigned long __force)port, dst, count);
+}
+
+static inline void _davinci_iowrite8(u8 value, void __iomem *port)
+{
+ _davinci_outb(value, (unsigned long __force)port);
+}
+
+static inline void _davinci_iowrite8_rep(void __iomem *port, const void *src,
+ unsigned long count)
+{
+ _davinci_outsb((unsigned long __force)port, src, count);
+}
+
+static inline void _davinci_iowrite16(u16 value, void __iomem *port)
+{
+ _davinci_outw(value, (unsigned long __force)port);
+}
+
+static inline void _davinci_iowrite16_rep(void __iomem *port, const void *src,
+ unsigned long count)
+{
+ _davinci_outsw((unsigned long __force)port, src, count);
+}
+
+static inline void _davinci_iowrite32(u32 value, void __iomem *port)
+{
+ _davinci_outl(value, (unsigned long __force)port);
+}
+
+static inline void _davinci_iowrite32_rep(void __iomem *port, const void *src,
+ unsigned long count)
+{
+ _davinci_outsl((unsigned long __force)port, src, count);
+}
+
+#define ioread8(p) _davinci_ioread8(p)
+#define ioread16(p) _davinci_ioread16(p)
+#define ioread32(p) _davinci_ioread32(p)
+
+#define iowrite8(v, p) _davinci_iowrite8(v, p)
+#define iowrite16(v, p) _davinci_iowrite16(v, p)
+#define iowrite32(v, p) _davinci_iowrite32(v, p)
+
+#define ioread8_rep(p, d, c) _davinci_ioread8_rep(p, d, c)
+#define ioread16_rep(p, d, c) _davinci_ioread8_rep(p, d, c)
+#define ioread32_rep(p, d, c) _davinci_ioread8_rep(p, d, c)
+
+#define iowrite8_rep(p, s, c) _davinci_iowrite8_rep(p, s, c)
+#define iowrite16_rep(p, s, c) _davinci_iowrite16_rep(p, s, c)
+#define iowrite32_rep(p, s, c) _davinci_iowrite32_rep(p, s, c)
+
+#define ioport_map(port, nr) ((void __iomem *)port)
+#define ioport_unmap(addr)
+
+#else /* !CONFIG_PCI */
+#define __io(a) __typesafe_io(a)
+#endif /* !CONFIG_PCI */
#ifdef __ASSEMBLER__
#define IOMEM(x) x
diff --git a/arch/arm/mach-davinci/include/mach/mux.h
b/arch/arm/mach-davinci/include/mach/mux.h
old mode 100644
new mode 100755
index 018701f..7c21022
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -94,9 +94,15 @@ enum davinci_dm646x_index {
/* ATA function */
DM646X_ATAEN,
+ /* PCI function */
+ DM646X_PCIEN,
+
+ /* HPI 32-bit */
+ DM646X_HPI32EN,
+
/* AUDIO Clock */
- DM646X_AUDCK1,
- DM646X_AUDCK0,
+ DM646X_AUDCK1_DISABLE,
+ DM646X_AUDCK0_DISABLE,
/* CRGEN Control */
DM646X_CRGMUX,
diff --git a/arch/arm/mach-davinci/include/mach/serial.h
b/arch/arm/mach-davinci/include/mach/serial.h
old mode 100644
new mode 100755
index 794fa5c..36c63f3
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,7 +11,7 @@
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
-#include <mach/io.h>
+#include <mach/hardware.h>
#define DAVINCI_MAX_NR_UARTS 3
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h
b/arch/arm/mach-davinci/include/mach/vmalloc.h
old mode 100644
new mode 100755
index ad51625..d49646a
--- a/arch/arm/mach-davinci/include/mach/vmalloc.h
+++ b/arch/arm/mach-davinci/include/mach/vmalloc.h
@@ -8,7 +8,7 @@
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
-#include <mach/io.h>
+#include <mach/hardware.h>
/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
#define VMALLOC_END (IO_VIRT - (2<<20))
--
1.6.2.4
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