Troy Kisky wrote: > [email protected] wrote: >> From: Sneha Narnakaje <[email protected]> >> >> This patch adds 4-bit ECC support for large page NAND chips using the new ECC >> mode NAND_ECC_HW_OOB_FIRST. The platform data from board-dm355-evm has been >> adjusted to use this mode. >> >> The patches have been verified on DM355 device with 2K Micron devices using >> mtd-tests and JFFS2. Error correction upto 4-bits has also been verified >> using >> nandwrite/nanddump utilities. >> >> Reviewed-by: David Brownell <[email protected]> >> Signed-off-by: Sneha Narnakaje <[email protected]> >> --- >> drivers/mtd/nand/davinci_nand.c | 37 +++++++++++++++++++++++++++++++------ >> 1 files changed, 31 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/mtd/nand/davinci_nand.c >> b/drivers/mtd/nand/davinci_nand.c >> index ba6940d..4557b8d 100644 >> --- a/drivers/mtd/nand/davinci_nand.c >> +++ b/drivers/mtd/nand/davinci_nand.c >> @@ -689,15 +707,22 @@ static int __init nand_davinci_probe(struct >> platform_device *pdev) >> info->mtd.oobsize - 16; >> goto syndrome_done; >> } >> + if (chunks == 4) { >> + info->ecclayout = hwecc4_2048; >> + info->ecclayout.oobfree[1].length = >> + info->mtd.oobsize - 49; > Most drivers set chip->ecc.layout = ... Is it ok to use ecclayout instead?????
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