I modified 2.6.30-rc7 which was pulled from davinci git last week to
support our dm6446 board. In order to get i2s configured properly I had
to make some changes. There was no longer a definition for the CLKSM
bit. hwparams does not read the SRGR register, but instead simply sets
FSGM which is already set then configures the period and pulse width.
The datasheet does mention that ASP internal input clock is the default
mode on DSP reset, but I am not observing this. I assume that is
intended to be applicable to GPP boots DSP?
What would be the proper method for configuring the clock divider?
Other than values in hw_params... Settings from the machine driver or
something in the board support file?
First of all with respect to EDMA, I noticed initially that I no longer
encountered the problem I had previously had with the event not being
set for ASP when stopping and starting audio.
I ran a simple speaker-test loop which I had been using to test for
audio lockups previously and quickly encountered that condition. To see
if it was similar to what I had experienced before I added a 10ms delay
after edma stop to increase the latency between stopping and starting
edma and the issue (for the most part) went away. I verified that the
codec (tlv320dac2x) was configured properly and that the i2s clock was
active. At the point where it locks up, EDMA interrupts are no longer
generated on the ASP channel. I am at a loss as to what the real
failure condition here is. All I am doing is running (in two terminals).
while [ 1 ]; do speaker-test; done
while [ 1 ]; do killall speaker-test; usleep 200000; done
I have not tried this on the EVM with the latest GIT kernel and this is
a custom board so it's quite possible that the problem has something to
do with our specific design. Any insight is appreciated.
Thanks.
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