DA850/OMAP-L138 is the next generation DA830/OMAP-L137 processor from TI. DA830 and DA850 have many things in common. Instead of adding new files for DA850 reuse the existing DA830 files by renaming da830-xxx files to da8xx-xxx. Also rename common macros and functions that have da830 string in them to da8xx.
A new config variable CONFIG_ARCH_DAVINCI_DA8XX, is added to group DA830 and DA850 architectures. Signed-off-by: Sudhakar Rajashekhara <[email protected]> Signed-off-by: Sekhar Nori <[email protected]> --- arch/arm/mach-davinci/Kconfig | 4 + arch/arm/mach-davinci/Makefile | 2 +- arch/arm/mach-davinci/Makefile.boot | 4 +- arch/arm/mach-davinci/board-da830-evm.c | 14 +- arch/arm/mach-davinci/da830.c | 236 +++++++++--------- arch/arm/mach-davinci/devices-da830.c | 266 -------------------- arch/arm/mach-davinci/devices-da8xx.c | 280 ++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/da830.h | 69 ------ arch/arm/mach-davinci/include/mach/da8xx.h | 69 ++++++ arch/arm/mach-davinci/include/mach/debug-macro.S | 6 +- arch/arm/mach-davinci/include/mach/irqs.h | 148 ++++++------ arch/arm/mach-davinci/include/mach/memory.h | 6 +- arch/arm/mach-davinci/include/mach/psc.h | 70 +++--- arch/arm/mach-davinci/include/mach/serial.h | 6 +- arch/arm/mach-davinci/include/mach/uncompress.h | 2 +- 15 files changed, 602 insertions(+), 580 deletions(-) delete mode 100644 arch/arm/mach-davinci/devices-da830.c create mode 100644 arch/arm/mach-davinci/devices-da8xx.c delete mode 100644 arch/arm/mach-davinci/include/mach/da830.h create mode 100644 arch/arm/mach-davinci/include/mach/da8xx.h diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 0817adf..0a586ca 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -31,6 +31,10 @@ config ARCH_DAVINCI_DM646x config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137 based system" select CP_INTC + select ARCH_DAVINCI_DA8XX + +config ARCH_DAVINCI_DA8XX + bool config ARCH_DAVINCI_DM365 bool "DaVinci 365 based system" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 59b77a3..d183b11 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da830.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index 64e7824..db97ef2 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot @@ -1,6 +1,6 @@ -ifeq ($(CONFIG_ARCH_DAVINCI_DA830),y) +ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) -$(error Cannot enable DaVinci and DA830 platforms concurrently) +$(error Cannot enable DaVinci and DA8XX platforms concurrently) else zreladdr-y := 0xc0008000 params_phys-y := 0xc0000100 diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 09d01f4..0409eb6 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -22,7 +22,7 @@ #include <mach/common.h> #include <mach/irqs.h> #include <mach/cp_intc.h> -#include <mach/da830.h> +#include <mach/da8xx.h> #define DA830_EVM_PHY_MASK 0x0 #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -56,7 +56,7 @@ static __init void da830_evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; - ret = da830_register_edma(); + ret = da8xx_register_edma(); if (ret) pr_warning("da830_evm_init: edma registration failed: %d\n", ret); @@ -66,7 +66,7 @@ static __init void da830_evm_init(void) pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", ret); - ret = da830_register_i2c(0, &da830_evm_i2c_0_pdata); + ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); if (ret) pr_warning("da830_evm_init: i2c0 registration failed: %d\n", ret); @@ -80,12 +80,12 @@ static __init void da830_evm_init(void) pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", ret); - ret = da830_register_emac(); + ret = da8xx_register_emac(); if (ret) pr_warning("da830_evm_init: emac registration failed: %d\n", ret); - ret = da830_register_watchdog(); + ret = da8xx_register_watchdog(); if (ret) pr_warning("da830_evm_init: watchdog registration failed: %d\n", ret); @@ -107,7 +107,7 @@ static __init void da830_evm_irq_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; - cp_intc_init((void __iomem *)DA830_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, + cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, soc_info->intc_irq_prios); } @@ -119,7 +119,7 @@ static void __init da830_evm_map_io(void) MACHINE_START(DAVINCI_DA8XX_EVM, "DaVinci DA830/OMAP L137 EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, - .boot_params = (DA830_DDR_BASE + 0x100), + .boot_params = (DA8XX_DDR_BASE + 0x100), .map_io = da830_evm_map_io, .init_irq = da830_evm_irq_init, .timer = &davinci_timer, diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index ce8249a..ab42428 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -22,7 +22,7 @@ #include <mach/cputype.h> #include <mach/common.h> #include <mach/time.h> -#include <mach/da830.h> +#include <mach/da8xx.h> #include "clock.h" #include "mux.h" @@ -131,137 +131,137 @@ static struct clk timerp64_1_clk = { static struct clk arm_rom_clk = { .name = "arm_rom", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_ARM_RAM_ROM, + .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, .flags = ALWAYS_ENABLED, }; static struct clk scr0_ss_clk = { .name = "scr0_ss", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_SCR0_SS, + .lpsc = DA8XX_LPSC0_SCR0_SS, .flags = ALWAYS_ENABLED, }; static struct clk scr1_ss_clk = { .name = "scr1_ss", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_SCR1_SS, + .lpsc = DA8XX_LPSC0_SCR1_SS, .flags = ALWAYS_ENABLED, }; static struct clk scr2_ss_clk = { .name = "scr2_ss", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_SCR2_SS, + .lpsc = DA8XX_LPSC0_SCR2_SS, .flags = ALWAYS_ENABLED, }; static struct clk dmax_clk = { .name = "dmax", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_DMAX, + .lpsc = DA8XX_LPSC0_DMAX, .flags = ALWAYS_ENABLED, }; static struct clk tpcc_clk = { .name = "tpcc", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_TPCC, + .lpsc = DA8XX_LPSC0_TPCC, .flags = ALWAYS_ENABLED | CLK_PSC, }; static struct clk tptc0_clk = { .name = "tptc0", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_TPTC0, + .lpsc = DA8XX_LPSC0_TPTC0, .flags = ALWAYS_ENABLED, }; static struct clk tptc1_clk = { .name = "tptc1", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_TPTC1, + .lpsc = DA8XX_LPSC0_TPTC1, .flags = ALWAYS_ENABLED, }; static struct clk mmcsd_clk = { .name = "mmcsd", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_MMC_SD, + .lpsc = DA8XX_LPSC0_MMC_SD, }; static struct clk uart0_clk = { .name = "uart0", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_UART0, + .lpsc = DA8XX_LPSC0_UART0, }; static struct clk uart1_clk = { .name = "uart1", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_UART1, + .lpsc = DA8XX_LPSC1_UART1, .psc_ctlr = 1, }; static struct clk uart2_clk = { .name = "uart2", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_UART2, + .lpsc = DA8XX_LPSC1_UART2, .psc_ctlr = 1, }; static struct clk spi0_clk = { .name = "spi0", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC0_SPI0, + .lpsc = DA8XX_LPSC0_SPI0, }; static struct clk spi1_clk = { .name = "spi1", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_SPI1, + .lpsc = DA8XX_LPSC1_SPI1, .psc_ctlr = 1, }; static struct clk ecap0_clk = { .name = "ecap0", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_ECAP, + .lpsc = DA8XX_LPSC1_ECAP, .psc_ctlr = 1, }; static struct clk ecap1_clk = { .name = "ecap1", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_ECAP, + .lpsc = DA8XX_LPSC1_ECAP, .psc_ctlr = 1, }; static struct clk ecap2_clk = { .name = "ecap2", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_ECAP, + .lpsc = DA8XX_LPSC1_ECAP, .psc_ctlr = 1, }; static struct clk pwm0_clk = { .name = "pwm0", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_PWM, + .lpsc = DA8XX_LPSC1_PWM, .psc_ctlr = 1, }; static struct clk pwm1_clk = { .name = "pwm1", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_PWM, + .lpsc = DA8XX_LPSC1_PWM, .psc_ctlr = 1, }; static struct clk pwm2_clk = { .name = "pwm2", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_PWM, + .lpsc = DA8XX_LPSC1_PWM, .psc_ctlr = 1, }; @@ -282,14 +282,14 @@ static struct clk eqep1_clk = { static struct clk lcdc_clk = { .name = "lcdc", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_LCDC, + .lpsc = DA8XX_LPSC1_LCDC, .psc_ctlr = 1, }; static struct clk mcasp0_clk = { .name = "mcasp0", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_McASP0, + .lpsc = DA8XX_LPSC1_McASP0, .psc_ctlr = 1, }; @@ -310,63 +310,63 @@ static struct clk mcasp2_clk = { static struct clk usb20_clk = { .name = "usb20", .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_USB20, + .lpsc = DA8XX_LPSC1_USB20, .psc_ctlr = 1, }; static struct clk aemif_clk = { .name = "aemif", .parent = &pll0_sysclk3, - .lpsc = DA830_LPSC0_EMIF25, + .lpsc = DA8XX_LPSC0_EMIF25, .flags = ALWAYS_ENABLED, }; static struct clk aintc_clk = { .name = "aintc", .parent = &pll0_sysclk4, - .lpsc = DA830_LPSC0_AINTC, + .lpsc = DA8XX_LPSC0_AINTC, .flags = ALWAYS_ENABLED, }; static struct clk secu_mgr_clk = { .name = "secu_mgr", .parent = &pll0_sysclk4, - .lpsc = DA830_LPSC0_SECU_MGR, + .lpsc = DA8XX_LPSC0_SECU_MGR, .flags = ALWAYS_ENABLED, }; static struct clk emac_clk = { .name = "emac", .parent = &pll0_sysclk4, - .lpsc = DA830_LPSC1_CPGMAC, + .lpsc = DA8XX_LPSC1_CPGMAC, .psc_ctlr = 1, }; static struct clk gpio_clk = { .name = "gpio", .parent = &pll0_sysclk4, - .lpsc = DA830_LPSC1_GPIO, + .lpsc = DA8XX_LPSC1_GPIO, .psc_ctlr = 1, }; static struct clk i2c1_clk = { .name = "i2c1", .parent = &pll0_sysclk4, - .lpsc = DA830_LPSC1_I2C, + .lpsc = DA8XX_LPSC1_I2C, .psc_ctlr = 1, }; static struct clk usb11_clk = { .name = "usb11", .parent = &pll0_sysclk4, - .lpsc = DA830_LPSC1_USB11, + .lpsc = DA8XX_LPSC1_USB11, .psc_ctlr = 1, }; static struct clk emif3_clk = { .name = "emif3", .parent = &pll0_sysclk5, - .lpsc = DA830_LPSC1_EMIF3C, + .lpsc = DA8XX_LPSC1_EMIF3C, .flags = ALWAYS_ENABLED, .psc_ctlr = 1, }; @@ -374,7 +374,7 @@ static struct clk emif3_clk = { static struct clk arm_clk = { .name = "arm", .parent = &pll0_sysclk6, - .lpsc = DA830_LPSC0_ARM, + .lpsc = DA8XX_LPSC0_ARM, .flags = ALWAYS_ENABLED, }; @@ -1060,83 +1060,83 @@ int da830_pinmux_setup(const short pins[]) /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { - [IRQ_DA830_COMMTX] = 7, - [IRQ_DA830_COMMRX] = 7, - [IRQ_DA830_NINT] = 7, - [IRQ_DA830_EVTOUT0] = 7, - [IRQ_DA830_EVTOUT1] = 7, - [IRQ_DA830_EVTOUT2] = 7, - [IRQ_DA830_EVTOUT3] = 7, - [IRQ_DA830_EVTOUT4] = 7, - [IRQ_DA830_EVTOUT5] = 7, - [IRQ_DA830_EVTOUT6] = 7, - [IRQ_DA830_EVTOUT6] = 7, - [IRQ_DA830_EVTOUT7] = 7, - [IRQ_DA830_CCINT0] = 7, - [IRQ_DA830_CCERRINT] = 7, - [IRQ_DA830_TCERRINT0] = 7, - [IRQ_DA830_AEMIFINT] = 7, - [IRQ_DA830_I2CINT0] = 7, - [IRQ_DA830_MMCSDINT0] = 7, - [IRQ_DA830_MMCSDINT1] = 7, - [IRQ_DA830_ALLINT0] = 7, - [IRQ_DA830_RTC] = 7, - [IRQ_DA830_SPINT0] = 7, - [IRQ_DA830_TINT12_0] = 7, - [IRQ_DA830_TINT34_0] = 7, - [IRQ_DA830_TINT12_1] = 7, - [IRQ_DA830_TINT34_1] = 7, - [IRQ_DA830_UARTINT0] = 7, - [IRQ_DA830_KEYMGRINT] = 7, - [IRQ_DA830_SECINT] = 7, - [IRQ_DA830_SECKEYERR] = 7, + [IRQ_DA8XX_COMMTX] = 7, + [IRQ_DA8XX_COMMRX] = 7, + [IRQ_DA8XX_NINT] = 7, + [IRQ_DA8XX_EVTOUT0] = 7, + [IRQ_DA8XX_EVTOUT1] = 7, + [IRQ_DA8XX_EVTOUT2] = 7, + [IRQ_DA8XX_EVTOUT3] = 7, + [IRQ_DA8XX_EVTOUT4] = 7, + [IRQ_DA8XX_EVTOUT5] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT7] = 7, + [IRQ_DA8XX_CCINT0] = 7, + [IRQ_DA8XX_CCERRINT] = 7, + [IRQ_DA8XX_TCERRINT0] = 7, + [IRQ_DA8XX_AEMIFINT] = 7, + [IRQ_DA8XX_I2CINT0] = 7, + [IRQ_DA8XX_MMCSDINT0] = 7, + [IRQ_DA8XX_MMCSDINT1] = 7, + [IRQ_DA8XX_ALLINT0] = 7, + [IRQ_DA8XX_RTC] = 7, + [IRQ_DA8XX_SPINT0] = 7, + [IRQ_DA8XX_TINT12_0] = 7, + [IRQ_DA8XX_TINT34_0] = 7, + [IRQ_DA8XX_TINT12_1] = 7, + [IRQ_DA8XX_TINT34_1] = 7, + [IRQ_DA8XX_UARTINT0] = 7, + [IRQ_DA8XX_KEYMGRINT] = 7, + [IRQ_DA8XX_SECINT] = 7, + [IRQ_DA8XX_SECKEYERR] = 7, [IRQ_DA830_MPUERR] = 7, [IRQ_DA830_IOPUERR] = 7, [IRQ_DA830_BOOTCFGERR] = 7, - [IRQ_DA830_CHIPINT0] = 7, - [IRQ_DA830_CHIPINT1] = 7, - [IRQ_DA830_CHIPINT2] = 7, - [IRQ_DA830_CHIPINT3] = 7, - [IRQ_DA830_TCERRINT1] = 7, - [IRQ_DA830_C0_RX_THRESH_PULSE] = 7, - [IRQ_DA830_C0_RX_PULSE] = 7, - [IRQ_DA830_C0_TX_PULSE] = 7, - [IRQ_DA830_C0_MISC_PULSE] = 7, - [IRQ_DA830_C1_RX_THRESH_PULSE] = 7, - [IRQ_DA830_C1_RX_PULSE] = 7, - [IRQ_DA830_C1_TX_PULSE] = 7, - [IRQ_DA830_C1_MISC_PULSE] = 7, - [IRQ_DA830_MEMERR] = 7, - [IRQ_DA830_GPIO0] = 7, - [IRQ_DA830_GPIO1] = 7, - [IRQ_DA830_GPIO2] = 7, - [IRQ_DA830_GPIO3] = 7, - [IRQ_DA830_GPIO4] = 7, - [IRQ_DA830_GPIO5] = 7, - [IRQ_DA830_GPIO6] = 7, - [IRQ_DA830_GPIO7] = 7, - [IRQ_DA830_GPIO8] = 7, - [IRQ_DA830_I2CINT1] = 7, - [IRQ_DA830_LCDINT] = 7, - [IRQ_DA830_UARTINT1] = 7, - [IRQ_DA830_MCASPINT] = 7, - [IRQ_DA830_ALLINT1] = 7, - [IRQ_DA830_SPINT1] = 7, - [IRQ_DA830_UHPI_INT1] = 7, - [IRQ_DA830_USB_INT] = 7, - [IRQ_DA830_IRQN] = 7, - [IRQ_DA830_RWAKEUP] = 7, - [IRQ_DA830_UARTINT2] = 7, - [IRQ_DA830_DFTSSINT] = 7, - [IRQ_DA830_EHRPWM0] = 7, - [IRQ_DA830_EHRPWM0TZ] = 7, - [IRQ_DA830_EHRPWM1] = 7, - [IRQ_DA830_EHRPWM1TZ] = 7, + [IRQ_DA8XX_CHIPINT0] = 7, + [IRQ_DA8XX_CHIPINT1] = 7, + [IRQ_DA8XX_CHIPINT2] = 7, + [IRQ_DA8XX_CHIPINT3] = 7, + [IRQ_DA8XX_TCERRINT1] = 7, + [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C0_RX_PULSE] = 7, + [IRQ_DA8XX_C0_TX_PULSE] = 7, + [IRQ_DA8XX_C0_MISC_PULSE] = 7, + [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C1_RX_PULSE] = 7, + [IRQ_DA8XX_C1_TX_PULSE] = 7, + [IRQ_DA8XX_C1_MISC_PULSE] = 7, + [IRQ_DA8XX_MEMERR] = 7, + [IRQ_DA8XX_GPIO0] = 7, + [IRQ_DA8XX_GPIO1] = 7, + [IRQ_DA8XX_GPIO2] = 7, + [IRQ_DA8XX_GPIO3] = 7, + [IRQ_DA8XX_GPIO4] = 7, + [IRQ_DA8XX_GPIO5] = 7, + [IRQ_DA8XX_GPIO6] = 7, + [IRQ_DA8XX_GPIO7] = 7, + [IRQ_DA8XX_GPIO8] = 7, + [IRQ_DA8XX_I2CINT1] = 7, + [IRQ_DA8XX_LCDINT] = 7, + [IRQ_DA8XX_UARTINT1] = 7, + [IRQ_DA8XX_MCASPINT] = 7, + [IRQ_DA8XX_ALLINT1] = 7, + [IRQ_DA8XX_SPINT1] = 7, + [IRQ_DA8XX_UHPI_INT1] = 7, + [IRQ_DA8XX_USB_INT] = 7, + [IRQ_DA8XX_IRQN] = 7, + [IRQ_DA8XX_RWAKEUP] = 7, + [IRQ_DA8XX_UARTINT2] = 7, + [IRQ_DA8XX_DFTSSINT] = 7, + [IRQ_DA8XX_EHRPWM0] = 7, + [IRQ_DA8XX_EHRPWM0TZ] = 7, + [IRQ_DA8XX_EHRPWM1] = 7, + [IRQ_DA8XX_EHRPWM1TZ] = 7, [IRQ_DA830_EHRPWM2] = 7, [IRQ_DA830_EHRPWM2TZ] = 7, - [IRQ_DA830_ECAP0] = 7, - [IRQ_DA830_ECAP1] = 7, - [IRQ_DA830_ECAP2] = 7, + [IRQ_DA8XX_ECAP0] = 7, + [IRQ_DA8XX_ECAP1] = 7, + [IRQ_DA8XX_ECAP2] = 7, [IRQ_DA830_EQEP0] = 7, [IRQ_DA830_EQEP1] = 7, [IRQ_DA830_T12CMPINT0_0] = 7, @@ -1155,7 +1155,7 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { [IRQ_DA830_T12CMPINT5_1] = 7, [IRQ_DA830_T12CMPINT6_1] = 7, [IRQ_DA830_T12CMPINT7_1] = 7, - [IRQ_DA830_ARMCLKSTOPREQ] = 7, + [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, }; static struct map_desc da830_io_desc[] = { @@ -1166,9 +1166,9 @@ static struct map_desc da830_io_desc[] = { .type = MT_DEVICE }, { - .virtual = DA830_CP_INTC_VIRT, - .pfn = __phys_to_pfn(DA830_CP_INTC_BASE), - .length = DA830_CP_INTC_SIZE, + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, .type = MT_DEVICE }, }; @@ -1192,15 +1192,15 @@ static struct davinci_id da830_ids[] = { static struct davinci_timer_instance da830_timer_instance[2] = { { .base = IO_ADDRESS(DA830_TIMER64P0_BASE), - .bottom_irq = IRQ_DA830_TINT12_0, - .top_irq = IRQ_DA830_TINT34_0, + .bottom_irq = IRQ_DA8XX_TINT12_0, + .top_irq = IRQ_DA8XX_TINT34_0, .cmp_off = DA830_CMP12_0, .cmp_irq = IRQ_DA830_T12CMPINT0_0, }, { .base = IO_ADDRESS(DA830_TIMER64P1_BASE), - .bottom_irq = IRQ_DA830_TINT12_1, - .top_irq = IRQ_DA830_TINT34_1, + .bottom_irq = IRQ_DA8XX_TINT12_1, + .top_irq = IRQ_DA8XX_TINT34_1, .cmp_off = DA830_CMP12_0, .cmp_irq = IRQ_DA830_T12CMPINT0_1, }, @@ -1226,19 +1226,19 @@ static struct davinci_soc_info davinci_soc_info_da830 = { .cpu_clks = da830_clks, .psc_bases = da830_psc_bases, .psc_bases_num = ARRAY_SIZE(da830_psc_bases), - .pinmux_base = IO_ADDRESS(DA830_BOOT_CFG_BASE + 0x120), + .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), - .intc_base = (void __iomem *)DA830_CP_INTC_VIRT, + .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, .intc_type = DAVINCI_INTC_TYPE_CP_INTC, .intc_irq_prios = da830_default_priorities, .intc_irq_num = DA830_N_CP_INTC_IRQ, .timer_info = &da830_timer_info, .gpio_base = IO_ADDRESS(DA830_GPIO_BASE), .gpio_num = 128, - .gpio_irq = IRQ_DA830_GPIO0, - .serial_dev = &da830_serial_device, - .emac_pdata = &da830_emac_pdata, + .gpio_irq = IRQ_DA8XX_GPIO0, + .serial_dev = &da8xx_serial_device, + .emac_pdata = &da8xx_emac_pdata, }; void __init da830_init(void) diff --git a/arch/arm/mach-davinci/devices-da830.c b/arch/arm/mach-davinci/devices-da830.c deleted file mode 100644 index 95110ca..0000000 --- a/arch/arm/mach-davinci/devices-da830.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * DA830/OMAP L137 platform device data - * - * Copyright (c) 2007-2009, MontaVista Software, Inc. <[email protected]> - * Derived from code that was: - * Copyright (C) 2006 Komal Shah <[email protected]> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/serial_8250.h> - -#include <mach/cputype.h> -#include <mach/common.h> -#include <mach/time.h> -#include <mach/da830.h> - -#include "clock.h" - -#define DA830_TPCC_BASE 0x01c00000 -#define DA830_TPTC0_BASE 0x01c08000 -#define DA830_TPTC1_BASE 0x01c08400 -#define DA830_WDOG_BASE 0x01c21000 /* DA830_TIMER64P1_BASE */ -#define DA830_I2C0_BASE 0x01c22000 -#define DA830_EMAC_CPPI_PORT_BASE 0x01e20000 -#define DA830_EMAC_CPGMACSS_BASE 0x01e22000 -#define DA830_EMAC_CPGMAC_BASE 0x01e23000 -#define DA830_EMAC_MDIO_BASE 0x01e24000 -#define DA830_GPIO_BASE 0x01e26000 -#define DA830_I2C1_BASE 0x01e28000 - -#define DA830_EMAC_CTRL_REG_OFFSET 0x3000 -#define DA830_EMAC_MOD_REG_OFFSET 0x2000 -#define DA830_EMAC_RAM_OFFSET 0x0000 -#define DA830_MDIO_REG_OFFSET 0x4000 -#define DA830_EMAC_CTRL_RAM_SIZE SZ_8K - -static struct plat_serial8250_port da830_serial_pdata[] = { - { - .mapbase = DA830_UART0_BASE, - .irq = IRQ_DA830_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DA830_UART1_BASE, - .irq = IRQ_DA830_UARTINT1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DA830_UART2_BASE, - .irq = IRQ_DA830_UARTINT2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - }, -}; - -struct platform_device da830_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = da830_serial_pdata, - }, -}; - -static const s8 da830_dma_chan_no_event[] = { - 20, 21, - -1 -}; - -static struct edma_soc_info da830_edma_info = { - .n_channel = 32, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = da830_dma_chan_no_event, -}; - -static struct resource da830_edma_resources[] = { - { - .name = "edma_cc", - .start = DA830_TPCC_BASE, - .end = DA830_TPCC_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = DA830_TPTC0_BASE, - .end = DA830_TPTC0_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = DA830_TPTC1_BASE, - .end = DA830_TPTC1_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DA830_TCERRINT0, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DA830_CCERRINT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da830_edma_device = { - .name = "edma", - .id = -1, - .dev = { - .platform_data = &da830_edma_info, - }, - .num_resources = ARRAY_SIZE(da830_edma_resources), - .resource = da830_edma_resources, -}; - -int __init da830_register_edma(void) -{ - return platform_device_register(&da830_edma_device); -} - -static struct resource da830_i2c_resources0[] = { - { - .start = DA830_I2C0_BASE, - .end = DA830_I2C0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DA830_I2CINT0, - .end = IRQ_DA830_I2CINT0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da830_i2c_device0 = { - .name = "i2c_davinci", - .id = 1, - .num_resources = ARRAY_SIZE(da830_i2c_resources0), - .resource = da830_i2c_resources0, -}; - -static struct resource da830_i2c_resources1[] = { - { - .start = DA830_I2C1_BASE, - .end = DA830_I2C1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DA830_I2CINT1, - .end = IRQ_DA830_I2CINT1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da830_i2c_device1 = { - .name = "i2c_davinci", - .id = 2, - .num_resources = ARRAY_SIZE(da830_i2c_resources1), - .resource = da830_i2c_resources1, -}; - -int __init da830_register_i2c(int instance, - struct davinci_i2c_platform_data *pdata) -{ - struct platform_device *pdev; - - if (instance == 0) - pdev = &da830_i2c_device0; - else if (instance == 1) - pdev = &da830_i2c_device1; - else - return -EINVAL; - - pdev->dev.platform_data = pdata; - return platform_device_register(pdev); -} - -static struct resource da830_watchdog_resources[] = { - { - .start = DA830_WDOG_BASE, - .end = DA830_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device davinci_wdt_device = { - .name = "watchdog", - .id = -1, - .num_resources = ARRAY_SIZE(da830_watchdog_resources), - .resource = da830_watchdog_resources, -}; - -int __init da830_register_watchdog(void) -{ - return platform_device_register(&davinci_wdt_device); -} - -static struct resource da830_emac_resources[] = { - { - .start = DA830_EMAC_CPPI_PORT_BASE, - .end = DA830_EMAC_CPPI_PORT_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DA830_C0_RX_THRESH_PULSE, - .end = IRQ_DA830_C0_RX_THRESH_PULSE, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DA830_C0_RX_PULSE, - .end = IRQ_DA830_C0_RX_PULSE, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DA830_C0_TX_PULSE, - .end = IRQ_DA830_C0_TX_PULSE, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DA830_C0_MISC_PULSE, - .end = IRQ_DA830_C0_MISC_PULSE, - .flags = IORESOURCE_IRQ, - }, -}; - -struct emac_platform_data da830_emac_pdata = { - .ctrl_reg_offset = DA830_EMAC_CTRL_REG_OFFSET, - .ctrl_mod_reg_offset = DA830_EMAC_MOD_REG_OFFSET, - .ctrl_ram_offset = DA830_EMAC_RAM_OFFSET, - .mdio_reg_offset = DA830_MDIO_REG_OFFSET, - .ctrl_ram_size = DA830_EMAC_CTRL_RAM_SIZE, - .version = EMAC_VERSION_2, -}; - -static struct platform_device da830_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &da830_emac_pdata, - }, - .num_resources = ARRAY_SIZE(da830_emac_resources), - .resource = da830_emac_resources, -}; - -int __init da830_register_emac(void) -{ - return platform_device_register(&da830_emac_device); -} diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c new file mode 100644 index 0000000..b72f15b --- /dev/null +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -0,0 +1,280 @@ +/* + * DA8XX/OMAP L1XX platform device data + * + * Copyright (c) 2007-2009, MontaVista Software, Inc. <[email protected]> + * Derived from code that was: + * Copyright (C) 2006 Komal Shah <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/serial_8250.h> + +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/serial.h> +#include <mach/time.h> +#include <mach/da8xx.h> + +#include "clock.h" + +#define DA8XX_TPCC_BASE 0x01c00000 +#define DA8XX_TPTC0_BASE 0x01c08000 +#define DA8XX_TPTC1_BASE 0x01c08400 +#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ +#define DA8XX_I2C0_BASE 0x01c22000 +#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 +#define DA8XX_I2C1_BASE 0x01e28000 + +#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 +#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 +#define DA8XX_EMAC_RAM_OFFSET 0x0000 +#define DA8XX_MDIO_REG_OFFSET 0x4000 +#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K + +static struct plat_serial8250_port da8xx_serial_pdata[] = { + { + .mapbase = DA8XX_UART0_BASE, + .irq = IRQ_DA8XX_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DA8XX_UART1_BASE, + .irq = IRQ_DA8XX_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DA8XX_UART2_BASE, + .irq = IRQ_DA8XX_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0, + }, +}; + +struct platform_device da8xx_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = da8xx_serial_pdata, + }, +}; + +static const s8 da8xx_dma_chan_no_event[] = { + 20, 21, + -1 +}; + +static const s8 da8xx_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const s8 da8xx_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + +static struct edma_soc_info da8xx_edma_info = { + .n_channel = 32, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = da8xx_dma_chan_no_event, + .queue_tc_mapping = da8xx_queue_tc_mapping, + .queue_priority_mapping = da8xx_queue_priority_mapping, +}; + +static struct resource da8xx_edma_resources[] = { + { + .name = "edma_cc0", + .start = DA8XX_TPCC_BASE, + .end = DA8XX_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = DA8XX_TPTC0_BASE, + .end = DA8XX_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = DA8XX_TPTC1_BASE, + .end = DA8XX_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_TCERRINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_CCERRINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_edma_device = { + .name = "edma", + .id = 0, + .dev = { + .platform_data = &da8xx_edma_info, + }, + .num_resources = ARRAY_SIZE(da8xx_edma_resources), + .resource = da8xx_edma_resources, +}; + +int __init da8xx_register_edma(void) +{ + return platform_device_register(&da8xx_edma_device); +} + +static struct resource da8xx_i2c_resources0[] = { + { + .start = DA8XX_I2C0_BASE, + .end = DA8XX_I2C0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_I2CINT0, + .end = IRQ_DA8XX_I2CINT0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_i2c_device0 = { + .name = "i2c_davinci", + .id = 1, + .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), + .resource = da8xx_i2c_resources0, +}; + +static struct resource da8xx_i2c_resources1[] = { + { + .start = DA8XX_I2C1_BASE, + .end = DA8XX_I2C1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_I2CINT1, + .end = IRQ_DA8XX_I2CINT1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_i2c_device1 = { + .name = "i2c_davinci", + .id = 2, + .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), + .resource = da8xx_i2c_resources1, +}; + +int __init da8xx_register_i2c(int instance, + struct davinci_i2c_platform_data *pdata) +{ + struct platform_device *pdev; + + if (instance == 0) + pdev = &da8xx_i2c_device0; + else if (instance == 1) + pdev = &da8xx_i2c_device1; + else + return -EINVAL; + + pdev->dev.platform_data = pdata; + return platform_device_register(pdev); +} + +static struct resource da8xx_watchdog_resources[] = { + { + .start = DA8XX_WDOG_BASE, + .end = DA8XX_WDOG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device davinci_wdt_device = { + .name = "watchdog", + .id = -1, + .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), + .resource = da8xx_watchdog_resources, +}; + +int __init da8xx_register_watchdog(void) +{ + return platform_device_register(&davinci_wdt_device); +} + +static struct resource da8xx_emac_resources[] = { + { + .start = DA8XX_EMAC_CPPI_PORT_BASE, + .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x47ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, + .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_RX_PULSE, + .end = IRQ_DA8XX_C0_RX_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_TX_PULSE, + .end = IRQ_DA8XX_C0_TX_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_MISC_PULSE, + .end = IRQ_DA8XX_C0_MISC_PULSE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct emac_platform_data da8xx_emac_pdata = { + .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, + .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, + .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, + .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, + .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, + .version = EMAC_VERSION_2, +}; + +static struct platform_device da8xx_emac_device = { + .name = "davinci_emac", + .id = 1, + .dev = { + .platform_data = &da8xx_emac_pdata, + }, + .num_resources = ARRAY_SIZE(da8xx_emac_resources), + .resource = da8xx_emac_resources, +}; + +int __init da8xx_register_emac(void) +{ + return platform_device_register(&da8xx_emac_device); +} diff --git a/arch/arm/mach-davinci/include/mach/da830.h b/arch/arm/mach-davinci/include/mach/da830.h deleted file mode 100644 index 5c7196f..0000000 --- a/arch/arm/mach-davinci/include/mach/da830.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Chip specific defines for DA830/OMAP L137 SoC - * - * Author: Mark A. Greer <[email protected]> - * - * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_DAVINCI_DA830_H -#define __ASM_ARCH_DAVINCI_DA830_H - -#include <mach/serial.h> -#include <mach/edma.h> -#include <mach/i2c.h> -#include <mach/emac.h> - -/* - * The cp_intc interrupt controller for the da830 isn't in the same - * chunk of physical memory space as the other registers (like it is - * on the davincis) so it needs to be mapped separately. It will be - * mapped early on when the I/O space is mapped and we'll put it just - * before the I/O space in the processor's virtual memory space. - */ -#define DA830_CP_INTC_BASE 0xfffee000 -#define DA830_CP_INTC_SIZE SZ_8K -#define DA830_CP_INTC_VIRT (IO_VIRT - DA830_CP_INTC_SIZE - SZ_4K) - -#define DA830_BOOT_CFG_BASE (IO_PHYS + 0x14000) - -void __init da830_init(void); - -int da830_register_edma(void); -int da830_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); -int da830_register_watchdog(void); -int da830_register_emac(void); - -extern struct platform_device da830_serial_device; -extern struct emac_platform_data da830_emac_pdata; - -extern const short da830_emif25_pins[]; -extern const short da830_spi0_pins[]; -extern const short da830_spi1_pins[]; -extern const short da830_mmc_sd_pins[]; -extern const short da830_uart0_pins[]; -extern const short da830_uart1_pins[]; -extern const short da830_uart2_pins[]; -extern const short da830_usb20_pins[]; -extern const short da830_usb11_pins[]; -extern const short da830_uhpi_pins[]; -extern const short da830_cpgmac_pins[]; -extern const short da830_emif3c_pins[]; -extern const short da830_mcasp0_pins[]; -extern const short da830_mcasp1_pins[]; -extern const short da830_mcasp2_pins[]; -extern const short da830_i2c0_pins[]; -extern const short da830_i2c1_pins[]; -extern const short da830_lcdcntl_pins[]; -extern const short da830_pwm_pins[]; -extern const short da830_ecap0_pins[]; -extern const short da830_ecap1_pins[]; -extern const short da830_ecap2_pins[]; -extern const short da830_eqep0_pins[]; -extern const short da830_eqep1_pins[]; - -int da830_pinmux_setup(const short pins[]); - -#endif /* __ASM_ARCH_DAVINCI_DA830_H */ diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 0000000..084db27 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -0,0 +1,69 @@ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <[email protected]> + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include <mach/serial.h> +#include <mach/edma.h> +#include <mach/i2c.h> +#include <mach/emac.h> + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) + +void __init da830_init(void); + +int da8xx_register_edma(void); +int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); +int da8xx_register_watchdog(void); +int da8xx_register_emac(void); + +extern struct platform_device da8xx_serial_device; +extern struct emac_platform_data da8xx_emac_pdata; + +extern const short da830_emif25_pins[]; +extern const short da830_spi0_pins[]; +extern const short da830_spi1_pins[]; +extern const short da830_mmc_sd_pins[]; +extern const short da830_uart0_pins[]; +extern const short da830_uart1_pins[]; +extern const short da830_uart2_pins[]; +extern const short da830_usb20_pins[]; +extern const short da830_usb11_pins[]; +extern const short da830_uhpi_pins[]; +extern const short da830_cpgmac_pins[]; +extern const short da830_emif3c_pins[]; +extern const short da830_mcasp0_pins[]; +extern const short da830_mcasp1_pins[]; +extern const short da830_mcasp2_pins[]; +extern const short da830_i2c0_pins[]; +extern const short da830_i2c1_pins[]; +extern const short da830_lcdcntl_pins[]; +extern const short da830_pwm_pins[]; +extern const short da830_ecap0_pins[]; +extern const short da830_ecap1_pins[]; +extern const short da830_ecap2_pins[]; +extern const short da830_eqep0_pins[]; +extern const short da830_eqep1_pins[]; + +int da830_pinmux_setup(const short pins[]); + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 6cb21e0..642f000 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -24,9 +24,9 @@ tst \rx, #1 @ MMU enabled? moveq \rx, #0x01000000 @ physical base address movne \rx, #0xfe000000 @ virtual base -#if defined(CONFIG_ARCH_DAVINCI_DA830) && defined(CONFIG_ARCH_DAVINCI_DMx) -#error Cannot enable DaVinci and DA830 platforms concurrently -#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_ARCH_DAVINCI_DA8XX) orr \rx, \rx, #0x00d00000 @ physical base address orr \rx, \rx, #0x0000d000 @ of UART 2 #else diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index fa0b204..ec9012f 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -239,83 +239,86 @@ #define IRQ_DM365_TCERRINT3 62 #define IRQ_DM365_EMUINT 63 -/* DA830 interrupts */ -#define IRQ_DA830_COMMTX 0 -#define IRQ_DA830_COMMRX 1 -#define IRQ_DA830_NINT 2 -#define IRQ_DA830_EVTOUT0 3 -#define IRQ_DA830_EVTOUT1 4 -#define IRQ_DA830_EVTOUT2 5 -#define IRQ_DA830_EVTOUT3 6 -#define IRQ_DA830_EVTOUT4 7 -#define IRQ_DA830_EVTOUT5 8 -#define IRQ_DA830_EVTOUT6 9 -#define IRQ_DA830_EVTOUT7 10 -#define IRQ_DA830_CCINT0 11 -#define IRQ_DA830_CCERRINT 12 -#define IRQ_DA830_TCERRINT0 13 -#define IRQ_DA830_AEMIFINT 14 -#define IRQ_DA830_I2CINT0 15 -#define IRQ_DA830_MMCSDINT0 16 -#define IRQ_DA830_MMCSDINT1 17 -#define IRQ_DA830_ALLINT0 18 -#define IRQ_DA830_RTC 19 -#define IRQ_DA830_SPINT0 20 -#define IRQ_DA830_TINT12_0 21 -#define IRQ_DA830_TINT34_0 22 -#define IRQ_DA830_TINT12_1 23 -#define IRQ_DA830_TINT34_1 24 -#define IRQ_DA830_UARTINT0 25 -#define IRQ_DA830_KEYMGRINT 26 -#define IRQ_DA830_SECINT 26 -#define IRQ_DA830_SECKEYERR 26 +/* DA8XX Interrupts */ +#define IRQ_DA8XX_COMMTX 0 +#define IRQ_DA8XX_COMMRX 1 +#define IRQ_DA8XX_NINT 2 +#define IRQ_DA8XX_EVTOUT0 3 +#define IRQ_DA8XX_EVTOUT1 4 +#define IRQ_DA8XX_EVTOUT2 5 +#define IRQ_DA8XX_EVTOUT3 6 +#define IRQ_DA8XX_EVTOUT4 7 +#define IRQ_DA8XX_EVTOUT5 8 +#define IRQ_DA8XX_EVTOUT6 9 +#define IRQ_DA8XX_EVTOUT7 10 +#define IRQ_DA8XX_CCINT0 11 +#define IRQ_DA8XX_CCERRINT 12 +#define IRQ_DA8XX_TCERRINT0 13 +#define IRQ_DA8XX_AEMIFINT 14 +#define IRQ_DA8XX_I2CINT0 15 +#define IRQ_DA8XX_MMCSDINT0 16 +#define IRQ_DA8XX_MMCSDINT1 17 +#define IRQ_DA8XX_ALLINT0 18 +#define IRQ_DA8XX_RTC 19 +#define IRQ_DA8XX_SPINT0 20 +#define IRQ_DA8XX_TINT12_0 21 +#define IRQ_DA8XX_TINT34_0 22 +#define IRQ_DA8XX_TINT12_1 23 +#define IRQ_DA8XX_TINT34_1 24 +#define IRQ_DA8XX_UARTINT0 25 +#define IRQ_DA8XX_KEYMGRINT 26 +#define IRQ_DA8XX_SECINT 26 +#define IRQ_DA8XX_SECKEYERR 26 +#define IRQ_DA8XX_CHIPINT0 28 +#define IRQ_DA8XX_CHIPINT1 29 +#define IRQ_DA8XX_CHIPINT2 30 +#define IRQ_DA8XX_CHIPINT3 31 +#define IRQ_DA8XX_TCERRINT1 32 +#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 +#define IRQ_DA8XX_C0_RX_PULSE 34 +#define IRQ_DA8XX_C0_TX_PULSE 35 +#define IRQ_DA8XX_C0_MISC_PULSE 36 +#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 +#define IRQ_DA8XX_C1_RX_PULSE 38 +#define IRQ_DA8XX_C1_TX_PULSE 39 +#define IRQ_DA8XX_C1_MISC_PULSE 40 +#define IRQ_DA8XX_MEMERR 41 +#define IRQ_DA8XX_GPIO0 42 +#define IRQ_DA8XX_GPIO1 43 +#define IRQ_DA8XX_GPIO2 44 +#define IRQ_DA8XX_GPIO3 45 +#define IRQ_DA8XX_GPIO4 46 +#define IRQ_DA8XX_GPIO5 47 +#define IRQ_DA8XX_GPIO6 48 +#define IRQ_DA8XX_GPIO7 49 +#define IRQ_DA8XX_GPIO8 50 +#define IRQ_DA8XX_I2CINT1 51 +#define IRQ_DA8XX_LCDINT 52 +#define IRQ_DA8XX_UARTINT1 53 +#define IRQ_DA8XX_MCASPINT 54 +#define IRQ_DA8XX_ALLINT1 55 +#define IRQ_DA8XX_SPINT1 56 +#define IRQ_DA8XX_UHPI_INT1 57 +#define IRQ_DA8XX_USB_INT 58 +#define IRQ_DA8XX_IRQN 59 +#define IRQ_DA8XX_RWAKEUP 60 +#define IRQ_DA8XX_UARTINT2 61 +#define IRQ_DA8XX_DFTSSINT 62 +#define IRQ_DA8XX_EHRPWM0 63 +#define IRQ_DA8XX_EHRPWM0TZ 64 +#define IRQ_DA8XX_EHRPWM1 65 +#define IRQ_DA8XX_EHRPWM1TZ 66 +#define IRQ_DA8XX_ECAP0 69 +#define IRQ_DA8XX_ECAP1 70 +#define IRQ_DA8XX_ECAP2 71 +#define IRQ_DA8XX_ARMCLKSTOPREQ 90 + +/* DA830 specific interrupts */ #define IRQ_DA830_MPUERR 27 #define IRQ_DA830_IOPUERR 27 #define IRQ_DA830_BOOTCFGERR 27 -#define IRQ_DA830_CHIPINT0 28 -#define IRQ_DA830_CHIPINT1 29 -#define IRQ_DA830_CHIPINT2 30 -#define IRQ_DA830_CHIPINT3 31 -#define IRQ_DA830_TCERRINT1 32 -#define IRQ_DA830_C0_RX_THRESH_PULSE 33 -#define IRQ_DA830_C0_RX_PULSE 34 -#define IRQ_DA830_C0_TX_PULSE 35 -#define IRQ_DA830_C0_MISC_PULSE 36 -#define IRQ_DA830_C1_RX_THRESH_PULSE 37 -#define IRQ_DA830_C1_RX_PULSE 38 -#define IRQ_DA830_C1_TX_PULSE 39 -#define IRQ_DA830_C1_MISC_PULSE 40 -#define IRQ_DA830_MEMERR 41 -#define IRQ_DA830_GPIO0 42 -#define IRQ_DA830_GPIO1 43 -#define IRQ_DA830_GPIO2 44 -#define IRQ_DA830_GPIO3 45 -#define IRQ_DA830_GPIO4 46 -#define IRQ_DA830_GPIO5 47 -#define IRQ_DA830_GPIO6 48 -#define IRQ_DA830_GPIO7 49 -#define IRQ_DA830_GPIO8 50 -#define IRQ_DA830_I2CINT1 51 -#define IRQ_DA830_LCDINT 52 -#define IRQ_DA830_UARTINT1 53 -#define IRQ_DA830_MCASPINT 54 -#define IRQ_DA830_ALLINT1 55 -#define IRQ_DA830_SPINT1 56 -#define IRQ_DA830_UHPI_INT1 57 -#define IRQ_DA830_USB_INT 58 -#define IRQ_DA830_IRQN 59 -#define IRQ_DA830_RWAKEUP 60 -#define IRQ_DA830_UARTINT2 61 -#define IRQ_DA830_DFTSSINT 62 -#define IRQ_DA830_EHRPWM0 63 -#define IRQ_DA830_EHRPWM0TZ 64 -#define IRQ_DA830_EHRPWM1 65 -#define IRQ_DA830_EHRPWM1TZ 66 #define IRQ_DA830_EHRPWM2 67 #define IRQ_DA830_EHRPWM2TZ 68 -#define IRQ_DA830_ECAP0 69 -#define IRQ_DA830_ECAP1 70 -#define IRQ_DA830_ECAP2 71 #define IRQ_DA830_EQEP0 72 #define IRQ_DA830_EQEP1 73 #define IRQ_DA830_T12CMPINT0_0 74 @@ -334,7 +337,6 @@ #define IRQ_DA830_T12CMPINT5_1 87 #define IRQ_DA830_T12CMPINT6_1 88 #define IRQ_DA830_T12CMPINT7_1 89 -#define IRQ_DA830_ARMCLKSTOPREQ 90 #define DA830_N_CP_INTC_IRQ 96 diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index b627d5e..ae902a3 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -21,12 +21,12 @@ * Definitions **************************************************************************/ #define DAVINCI_DDR_BASE 0x80000000 -#define DA830_DDR_BASE 0xc0000000 +#define DA8XX_DDR_BASE 0xc0000000 #if defined(CONFIG_ARCH_DAVINCI_DA830) && defined(CONFIG_ARCH_DAVINCI_DMx) #error Cannot enable DaVinci and DA830 platforms concurrently -#elif defined(CONFIG_ARCH_DAVINCI_DA830) -#define PHYS_OFFSET DA830_DDR_BASE +#elif defined(CONFIG_ARCH_DAVINCI_DA8XX) +#define PHYS_OFFSET DA8XX_DDR_BASE #else #define PHYS_OFFSET DAVINCI_DDR_BASE #endif diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 804a353..6b9621d 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -136,44 +136,46 @@ #define DM646X_LPSC_TIMER1 35 #define DM646X_LPSC_ARM_INTC 45 -#define DA830_LPSC0_TPCC 0 -#define DA830_LPSC0_TPTC0 1 -#define DA830_LPSC0_TPTC1 2 -#define DA830_LPSC0_EMIF25 3 -#define DA830_LPSC0_SPI0 4 -#define DA830_LPSC0_MMC_SD 5 -#define DA830_LPSC0_AINTC 6 -#define DA830_LPSC0_ARM_RAM_ROM 7 -#define DA830_LPSC0_SECU_MGR 8 -#define DA830_LPSC0_UART0 9 -#define DA830_LPSC0_SCR0_SS 10 -#define DA830_LPSC0_SCR1_SS 11 -#define DA830_LPSC0_SCR2_SS 12 -#define DA830_LPSC0_DMAX 13 -#define DA830_LPSC0_ARM 14 -#define DA830_LPSC0_GEM 15 +/* PSC0 defines */ +#define DA8XX_LPSC0_TPCC 0 +#define DA8XX_LPSC0_TPTC0 1 +#define DA8XX_LPSC0_TPTC1 2 +#define DA8XX_LPSC0_EMIF25 3 +#define DA8XX_LPSC0_SPI0 4 +#define DA8XX_LPSC0_MMC_SD 5 +#define DA8XX_LPSC0_AINTC 6 +#define DA8XX_LPSC0_ARM_RAM_ROM 7 +#define DA8XX_LPSC0_SECU_MGR 8 +#define DA8XX_LPSC0_UART0 9 +#define DA8XX_LPSC0_SCR0_SS 10 +#define DA8XX_LPSC0_SCR1_SS 11 +#define DA8XX_LPSC0_SCR2_SS 12 +#define DA8XX_LPSC0_DMAX 13 +#define DA8XX_LPSC0_ARM 14 +#define DA8XX_LPSC0_GEM 15 -#define DA830_LPSC1_USB20 1 -#define DA830_LPSC1_USB11 2 -#define DA830_LPSC1_GPIO 3 -#define DA830_LPSC1_UHPI 4 -#define DA830_LPSC1_CPGMAC 5 -#define DA830_LPSC1_EMIF3C 6 -#define DA830_LPSC1_McASP0 7 +/* PSC1 defines */ +#define DA8XX_LPSC1_USB20 1 +#define DA8XX_LPSC1_USB11 2 +#define DA8XX_LPSC1_GPIO 3 +#define DA8XX_LPSC1_UHPI 4 +#define DA8XX_LPSC1_CPGMAC 5 +#define DA8XX_LPSC1_EMIF3C 6 +#define DA8XX_LPSC1_McASP0 7 #define DA830_LPSC1_McASP1 8 #define DA830_LPSC1_McASP2 9 -#define DA830_LPSC1_SPI1 10 -#define DA830_LPSC1_I2C 11 -#define DA830_LPSC1_UART1 12 -#define DA830_LPSC1_UART2 13 -#define DA830_LPSC1_LCDC 16 -#define DA830_LPSC1_PWM 17 -#define DA830_LPSC1_ECAP 20 +#define DA8XX_LPSC1_SPI1 10 +#define DA8XX_LPSC1_I2C 11 +#define DA8XX_LPSC1_UART1 12 +#define DA8XX_LPSC1_UART2 13 +#define DA8XX_LPSC1_LCDC 16 +#define DA8XX_LPSC1_PWM 17 +#define DA8XX_LPSC1_ECAP 20 #define DA830_LPSC1_EQEP 21 -#define DA830_LPSC1_SCR_P0_SS 24 -#define DA830_LPSC1_SCR_P1_SS 25 -#define DA830_LPSC1_CR_P3_SS 26 -#define DA830_LPSC1_L3_CBA_RAM 31 +#define DA8XX_LPSC1_SCR_P0_SS 24 +#define DA8XX_LPSC1_SCR_P1_SS 25 +#define DA8XX_LPSC1_CR_P3_SS 26 +#define DA8XX_LPSC1_L3_CBA_RAM 31 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 9f23faa..57e68e6 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -18,9 +18,9 @@ #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) -#define DA830_UART0_BASE (IO_PHYS + 0x042000) -#define DA830_UART1_BASE (IO_PHYS + 0x10c000) -#define DA830_UART2_BASE (IO_PHYS + 0x10d000) +#define DA8XX_UART0_BASE (IO_PHYS + 0x042000) +#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) +#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 860ed7a..0f1f12b 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -22,7 +22,7 @@ static u32 *uart; static u32 *get_uart_base(void) { if (__machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) - return (u32 *)DA830_UART2_BASE; + return (u32 *)DA8XX_UART2_BASE; else return (u32 *)DAVINCI_UART0_BASE; } -- 1.5.6 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
