Brian Rhodes wrote:
MV Pro 5.0 toolchain
Codec Engine 2.23.01
DSP/BIOS 5.33.05
XDCTOOLS 3.15.00.50
Framework Components 2.23.01
XDAIS 6.23
DSPLINK 1.61.03
CMEM (linuxutils) 2.23.01
The error message @0,123,595us: [+7 T:0x44643490 S:0x44642d74] OP -
Processor_create_d> Loading and starting DSP server
'mpeg2_dec_server.x64P' FAILED, status=[0x80008009] (look for error
code 'DSP_EBASE + 0x9' in
dsplink*/packages/dsplink/gpp/inc/usr/errbase.h) says...
/* The specified executable file could not be found. */
#define DSP_EFILE (DSP_EBASE + 0x9l)
Previously I had simply located the DSP binary in the CWD, but surely
I've missed something in the documentation and this is now incorrect.
Is there a different way of configuring the path? I recall something
from a much older version of CE where you could specify the absolute
path in the engine creation call.
I found that I had a conditional including an incorrect config for my
server which was using DSP/BIOS 5_33_02 and that was causing the problem
loading the server. I am now having an issue with my memory map (I
think). I am getting an error when starting up the first server on the
dsp (from dsplink).
cmem initialized 9 pools between 0x87800000 and
0x88000000
DSPLINK Module (1.61.03) created on Date: Jun 23 2009 Time: 13:56:46
Assertion failed (cBytes != 0). File :
/home/bgr/projects/cerberus/support/code1
Assertion failed (PMGR_MSGQ_IsInitialized == TRUE). File :
/home/bgr/projects/c3
Unable to handle kernel NULL pointer dereference at virtual address 00000000
I think it is using the wrong memory area since the real failure here
appears to be incorrect data in the memory table. One of the sizes
appears as 0 causing the setup to fail, which then causes an Oops on
shutdown freeing a NULL ptr.
I tried specifying the memory map in the application config as well.
@0,432,351us: [+2 T:0x40b02490 S:0x40b01d74] OP - Processor_create_d>
Adding DSP segment #0 to Link configuration: name='DDR2',
startAddress=0x8fa00000, sizeInBytes=0x400000, shared=1, syncd=0
@0,432,595us: [+2 T:0x40b02490 S:0x40b01d74] OP - Processor_create_d>
Adding DSP segment #1 to Link configuration: name='DSPLINKMEM',
startAddress=0x8fe00000, sizeInBytes=0x30000, shared=1, syncd=0
@0,432,803us: [+2 T:0x40b02490 S:0x40b01d74] OP - Processor_create_d>
Adding DSP segment #2 to Link configuration: name='RESET_VECTOR',
startAddress=0x8ff00000, sizeInBytes=0x80, shared=1, syncd=0
@0,433,007us: [+2 T:0x40b02490 S:0x40b01d74] OP - Processor_create_d>
Adding DSP segment #3 to Link configuration: name='POOLMEM',
startAddress=0x8fe30000, sizeInBytes=0xd0000, shared=1, syncd=0
@0,433,210us: [+2 T:0x40b02490 S:0x40b01d74] OP - Processor_create_d>
Adding DSP segment #4 to Link configuration: name='DDRALGHEAP',
startAddress=0x88000000, sizeInBytes=0x4000000, shared=0, syncd=0
@0,433,405us: [+2 T:0x40b02490 S:0x40b01d74] OP - Processor_create_d>
DODSPCTRL was=1; now=0
@0,435,559us: [+0 T:0x4001fbc0 S:0xbedd298c] ti.sdo.ce.osal.Sem -
Leaving Sem_post> sem[0x441c0]
@0,435,874us: [+0 T:0x4001fbc0 S:0xbedd296c] ti.sdo.ce.osal.Sem -
Entered Sem_pend> sem[0x441d8] timeout[0xffffffff]
Anyone had success with this version of dsplink on dm6446?
/** ============================================================================
* @file CFG_DM6446GEM_SHMEM.c
*
* @path $(DSPLINK)/config/all/
*
* @desc Defines the configuration information for DSP/BIOS LINK for the
* Davinci platform.
*
* @ver 1.61.03
* ============================================================================
* Copyright (c) Texas Instruments Incorporated 2002-2008
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied or provided.
* ============================================================================
*/
/* ----------------------------------- DSP/BIOS LINK Headers */
#include <dsplink.h>
#include <procdefs.h>
#if defined (__cplusplus)
EXTERN "C" {
#endif /* defined (__cplusplus) */
/** ============================================================================
* DSPLINK MEMORY SECTION DIAGRAM
*
* |--------------[ 0xXXXXXX00 ]---------------------------------|
* | |
* | RESET VECTOR (0x80) |
* | Last two nibbles must be zero |
* | |
* |-------------------------------------------------------------|
* | |
* | DSP CODE/DATA |
* | DSP executable is loaded to this section |
* | |
* |=============================================================|
* | |
* | DSPLINK SHARED MEMORY0 |
* | Shared control structure is loaded here |
* | |
* |-------------------------------------------------------------|
* | |
* | DSPLINK SHARED MEMORY1 |
* | Shared control structure is loaded here |
* | |
* |-------------------------------------------------------------|
* | |
* | POOL Buffer Memory |
* | Pool's buffers are created in this area |
* | |
* |-------------------------------------------------------------|
*
* ============================================================================
*/
/** ============================================================================
* @name DRVHANDSHAKEPOLLCOUNT
*
* @desc POLL Count for Driver handshake.
* ============================================================================
*/
#define DRVHANDSHAKEPOLLCOUNT ((Uint32) 100000000u)
/** ============================================================================
* @name SHAREDENTRYID/SHAREDMEMORYADDR/SHAREDMEMORYSIZE
*
* @desc Indicates startaddress/size for dsplink shared memory region.
* ============================================================================
*/
#define SHAREDENTRYID0 0
#define SHAREDMEMORYADDR0 0x8FE00000
#define SHAREDMEMORYSIZE0 0x00005000u
/** ============================================================================
* @name SHAREDENTRYID/SHAREDMEMORYADDR/SHAREDMEMORYSIZE
*
* @desc Indicates startaddress/size for dsplink shared memory region.
* ============================================================================
*/
#define SHAREDENTRYID1 1
#define SHAREDMEMORYADDR1 0x8FE05000
#define SHAREDMEMORYSIZE1 0x0002B000u
/** ============================================================================
* @name RESETCTRLADDR
*
* @desc Indicates the start address of Reset Ctrl memory region.
* last two nibbles must be zero i.e. align to 256 boundary.
* ============================================================================
*/
#define RSTENTRYID 2
#define RESETCTRLADDR 0x8FF00000
#define RESETCTRLSIZE 0x00000080u
/** ============================================================================
* @name CODEMEMORYADDR/CODEMEMORYSIZE
*
* @desc Indicates startaddress/size for dsplink code region.
* ============================================================================
*/
#define CODEENTRYID 3
#define CODEMEMORYADDR 0x8FF00080
#define CODEMEMORYSIZE 0x000FFF80u
/** ============================================================================
* @name POOLMEMORYADDR/POOLMEMORYSIZE
*
* @desc Indicates startaddress/size for dsplink POOL memory region.
* ============================================================================
*/
#define POOLENTRYID 4
#define POOLMEMORYADDR (SHAREDMEMORYADDR1 + SHAREDMEMORYSIZE1)
#define POOLMEMORYSIZE 0x000D0000u
/** ============================================================================
* @name LINKCFG_memTable_00
*
* @desc Memory table ID 0.
* ============================================================================
*/
STATIC LINKCFG_MemEntry LINKCFG_memTable_00 [] =
{
{
SHAREDENTRYID0, /* ENTRY : Entry number */
"DSPLINKMEM", /* NAME : Name of the
memory region */
SHAREDMEMORYADDR0, /* ADDRPHYS : Physical address
*/
SHAREDMEMORYADDR0, /* ADDRDSPVIRT : DSP virtual
address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual
address (if known) */
SHAREDMEMORYSIZE0, /* SIZE : Size of the
memory region */
TRUE, /* SHARED : Shared access
memory? */
FALSE, /* SYNCD : Synchornized? */
},
{
SHAREDENTRYID1, /* ENTRY : Entry number */
"DSPLINKMEM1", /* NAME : Name of the
memory region */
SHAREDMEMORYADDR1, /* ADDRPHYS : Physical address
*/
SHAREDMEMORYADDR1, /* ADDRDSPVIRT : DSP virtual
address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual
address (if known) */
SHAREDMEMORYSIZE1, /* SIZE : Size of the
memory region */
TRUE, /* SHARED : Shared access
memory? */
FALSE, /* SYNCD : Synchornized? */
},
{
RSTENTRYID, /* ENTRY : Entry number */
"RESETCTRL", /* NAME : Name of the
memory region */
RESETCTRLADDR, /* ADDRPHYS : Physical address
*/
RESETCTRLADDR, /* ADDRDSPVIRT : DSP virtual
address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual
address (if known) */
RESETCTRLSIZE, /* SIZE : Size of the
memory region */
TRUE, /* SHARED : Shared access
memory? */
FALSE, /* SYNCD : Synchornized? */
},
{
CODEENTRYID, /* ENTRY : Entry number */
"DDR2", /* NAME : Name of the
memory region */
CODEMEMORYADDR, /* ADDRPHYS : Physical address
*/
CODEMEMORYADDR, /* ADDRDSPVIRT : DSP virtual
address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual
address (if known) */
CODEMEMORYSIZE, /* SIZE : Size of the
memory region */
TRUE, /* SHARED : Shared access
memory? */
FALSE, /* SYNCD : Synchornized? */
},
{
POOLENTRYID, /* ENTRY : Entry number */
"POOLMEM", /* NAME : Name of the
memory region */
POOLMEMORYADDR, /* ADDRPHYS : Physical address
*/
POOLMEMORYADDR, /* ADDRDSPVIRT : DSP virtual
address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual
address (if known) */
POOLMEMORYSIZE, /* SIZE : Size of the
memory region */
TRUE, /* SHARED : Shared access
memory? Logically */
FALSE, /* SYNCD : Synchornized? */
},
{
5, /* ENTRY : Entry number */
"DSPIRAM", /* NAME : Name of the memory region */
0x11800000, /* ADDRPHYS : Physical address */
0x11800000, /* ADDRDSPVIRT : DSP virtual address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual address (if
known) */
0x10000, /* SIZE : Size of the memory region */
TRUE, /* SHARED : Shared access memory? */
FALSE, /* SYNCD : Synchornized? */
},
{
6, /* ENTRY : Entry number */
"DSPL1DRAM", /* NAME : Name of the memory region */
0x11F04000, /* ADDRPHYS : Physical address */
0x11F04000, /* ADDRDSPVIRT : DSP virtual address */
(Uint32) -1, /* ADDRGPPVIRT : GPP virtual address (if
known) */
0xC000, /* SIZE : Size of the memory region */
TRUE, /* SHARED : Shared access memory? */
FALSE, /* SYNCD : Synchornized? */
},
} ;
/** ============================================================================
* @name LINKCFG_memTables
*
* @desc Array of memory tables in the system.
* ============================================================================
*/
STATIC LINKCFG_MemEntry * LINKCFG_memTables [] =
{
LINKCFG_memTable_00 /* Memory Table 0 */
} ;
/** ============================================================================
* @name LINKCFG_ipsTable_00
*
* @desc IPS table ID 0.
* ============================================================================
*/
STATIC LINKCFG_Ips LINKCFG_ipsTable_00 [] =
{
{
"IPS", /* NAME : Name of the
Inter-Processor-Signaling component */
(Uint32) 32, /* NUMIPSEVENTS : Number of IPS events to be
supported */
(Uint32) SHAREDENTRYID0, /* MEMENTRY : Memory entry ID (-1 if not
needed) */
(Uint32) 46, /* GPPINTID : Interrupt no. to used by
the IPS on GPP-side. (-1 if uni-directional to DSP) */
(Uint32) 16, /* DSPINTID : Interrupt no. to used by
the IPS on DSP-side. (-1 if uni-directional to GPP) */
(Uint32) 4, /* DSPINTVECTORID : Interrupt vector no. to
used by the IPS on DSP-side. (-1 if uni-directional to GPP) */
(Uint32) 50000000, /* ARGUMENT1 : Poll value for which IPS
waits while sending event (-1 if infinite) */
0 /* ARGUMENT2 : Second IPS-specific
argument */
},
{
"IPS", /* NAME : Name of the
Inter-Processor-Signaling component */
(Uint32) 32, /* MAXIPSEVENTS : Number of IPS events to be
supported */
(Uint32) SHAREDENTRYID1, /* MEMENTRY : Memory entry ID (-1 if not
needed) */
(Uint32) 47, /* GPPINTID : Interrupt no. to used by
the IPS on GPP-side. (-1 if uni-directional to DSP) */
(Uint32) 17, /* DSPINTID : Interrupt no. to used by
the IPS on DSP-side. (-1 if uni-directional to GPP) */
(Uint32) 5, /* DSPINTVECTORID : Interrupt vector no. to
used by the IPS on DSP-side. (-1 if uni-directional to GPP) */
(Uint32) 50000000, /* ARGUMENT1 : Poll value for which IPS
waits while sending event (-1 if infinite) */
0 /* ARGUMENT2 : Second IPS-specific
argument */
}
} ;
/** ============================================================================
* @name LINKCFG_ipsTables
*
* @desc Array of IPS tables in the system.
* ============================================================================
*/
STATIC LINKCFG_Ips * LINKCFG_ipsTables [] =
{
LINKCFG_ipsTable_00 /* IPS Table 0 */
} ;
/** ============================================================================
* @name LINKCFG_poolTable_00
*
* @desc Pool table ID 0.
* ============================================================================
*/
STATIC LINKCFG_Pool LINKCFG_poolTable_00 [] =
{
{
"SMAPOOL", /* NAME : Name of the pool */
(Uint32) SHAREDENTRYID1, /* MEMENTRY : Memory entry ID (-1 if
not needed) */
(Uint32) 0x70000, /* POOLSIZE : Size of the pool (-1 if
not needed) */
(Uint32) -1, /* IPSID : ID of the IPS used */
(Uint32) -1, /* IPSEVENTNO : IPS Event number
associated with POOL */
POOLENTRYID, /* POOLMEMENTRY : Pool memory region
section ID */
0x0, /* ARGUMENT1 : First Pool-specific
argument */
0x0 /* ARGUMENT2 : Second Pool-specific
argument */
}
} ;
/** ============================================================================
* @name LINKCFG_poolTables
*
* @desc Array of Pool tables in the system.
* ============================================================================
*/
STATIC LINKCFG_Pool * LINKCFG_poolTables [] =
{
LINKCFG_poolTable_00 /* Pool Table 0 */
} ;
/** ============================================================================
* @name LINKCFG_dataTable_00
*
* @desc Data driver table ID 0.
* ============================================================================
*/
STATIC LINKCFG_DataDrv LINKCFG_dataTable_00 [] =
{
{
"ZCPYDATA", /* NAME : Name of the data driver */
0, /* BASECHANNELID : Base channel ID for the
driver */
16, /* NUMCHANNELS : Number of channels
supported */
16384, /* MAXBUFSIZE : Maximum size of buffer
supported (-1 if no limit) */
(Uint32) SHAREDENTRYID1, /* MEMENTRY : Memory entry ID (-1 if not
needed) */
0, /* POOLID : Pool id for allocating
buffers */
1, /* QUEUELENGTH : Queue length for the data
driver */
1, /* IPSID : ID of the IPS used */
1, /* IPSEVENTNO : IPS Event number
associated with data Driver */
0x0, /* ARGUMENT1 : First data driver specific
argument */
0x0 /* ARGUMENT2 : Second data driver
specific argument */
}
} ;
/** ============================================================================
* @name LINKCFG_dataTables
*
* @desc Array of Data driver tables in the system.
* ============================================================================
*/
STATIC LINKCFG_DataDrv * LINKCFG_dataTables [] =
{
LINKCFG_dataTable_00 /* Data Table 0 */
} ;
/** ============================================================================
* @name LINKCFG_mqtObjects
*
* @desc Array of Message Queue Transport objects in the system.
* ============================================================================
*/
STATIC LINKCFG_Mqt LINKCFG_mqtObjects [] =
{
{
"ZCPYMQT", /* NAME : Name of the Message Queue
Transport */
(Uint32) SHAREDENTRYID1, /* MEMENTRY : Memory entry ID (-1 if
not needed) */
(Uint32) -1, /* MAXMSGSIZE : Maximum message size
supported (-1 if no limit) */
1, /* IPSID : ID of the IPS used */
0, /* IPSEVENTNO : IPS Event number
associated with MQT */
0x0, /* ARGUMENT1 : First MQT-specific
argument */
0x0 /* ARGUMENT2 : Second MQT-specific
argument */
}
} ;
/** ============================================================================
* @name LINKCFG_ringIoObjects
*
* @desc Array of RINGIO objects in the system.
* ============================================================================
*/
STATIC LINKCFG_RingIo LINKCFG_ringIoObjects [] =
{
{
"RINGIOTABLE", /* NAME : Name of the RingIO Table */
SHAREDENTRYID0, /* MEMENTRY : Memory entry ID (-1 if not needed)
*/
64, /* NUMENTRIES : Number of RingIO entries supported
*/
0, /* IPSID : ID of the IPS used */
0 /* IPSEVENTNO : IPS Event number associated with
RingIO */
}
} ;
/** ============================================================================
* @name LINKCFG_mplistObjects
*
* @desc Array of MPLIST objects in the system.
* ============================================================================
*/
STATIC LINKCFG_MpList LINKCFG_mplistObjects [] =
{
{
"MPLISTTABLE", /* NAME : Name of the MpList Table */
SHAREDENTRYID1, /* MEMENTRY : Memory entry ID (-1 if not
needed) */
64, /* NUMENTRIES : Number of MpList entries
supported */
(Uint32) -1, /* IPSID : ID of the IPS used */
(Uint32) -1 /* IPSEVENTNO : IPS Event number associated
with MpList */
}
} ;
/** ============================================================================
* @name LINKCFG_mpcsObjects
*
* @desc Array of MPCS objects in the system.
* ============================================================================
*/
STATIC LINKCFG_Mpcs LINKCFG_mpcsObjects [] =
{
{
"MPCS", /* NAME : Name of the MPCS Table */
SHAREDENTRYID1, /* MEMENTRY : Memory entry ID (-1 if not
needed) */
256, /* NUMENTRIES : Number of MPCS entries
supported */
(Uint32) -1, /* IPSID : ID of the IPS used */
(Uint32) -1 /* IPSEVENTNO : IPS Event number associated
with MPCS */
}
} ;
/** ============================================================================
* @name LINKCFG_gppObject
*
* @desc Configuration object for the GPP.
* ============================================================================
*/
STATIC LINKCFG_Log LINKCFG_logObject = {
FALSE, /* GDMSGQPUT : GPP->DSP MSG Transfer - MSGQ_put
call */
FALSE, /* GDMSGQSENDINT : GPP->DSP MSG Transfer - GPP
sends interrupt */
FALSE, /* GDMSGQISR : GPP->DSP MSG Transfer - DSP
receives interrupt */
FALSE, /* GDMSGQQUE : GPP->DSP MSG Transfer - Message
queued at DSP */
FALSE, /* DGMSGQPUT : DSP->GPP MSG Transfer - MSGQ_put
call */
FALSE, /* DGMSGQSENDINT : DSP->GPP MSG Transfer - DSP
sends interrupt */
FALSE, /* DGMSGQISR : DSP->GPP MSG Transfer - GPP
receives interrupt */
FALSE, /* DGMSGQQUE : DSP->GPP MSG Transfer - Message
queued at GPP */
FALSE, /* GDCHNLISSUESTART : GPP->DSP CHNL Transfer - Entering
inside ISSUE call */
FALSE, /* GDCHNLISSUEQUE : GPP->DSP CHNL Transfer - ISSUE:
Buffer is queued in internal structure on GPP */
FALSE, /* GDCHNLISSUECOMPL : GPP->DSP CHNL Transfer - ISSUE
call completed */
FALSE, /* GDCHNLXFERSTART : GPP->DSP CHNL Transfer -
Initiating a buffer transfer by GPP */
FALSE, /* GDCHNLXFERPROCESS : GPP->DSP CHNL Transfer - Actual
transfer of buffer is going to take place */
FALSE, /* GDCHNLXFERCOMPL : GPP->DSP CHNL Transfer - Buffer
transfer is complete */
FALSE, /* GDCHNLRECLSTART : GPP->DSP CHNL Transfer - Entering
RECLAIM call */
FALSE, /* GDCHNLRECLPEND : GPP->DSP CHNL Transfer - RECLAIM:
Wait on a semaphore */
FALSE, /* GDCHNLRECLPOST : GPP->DSP CHNL Transfer - RECLAIM:
Posting the Semaphore */
FALSE, /* GDCHNLRECLCOMPL : GPP->DSP CHNL Transfer - RECLAIM
call completed */
FALSE, /* DGCHNLISSUEQUE : DSP->GPP CHNL Transfer - ISSUE:
Buffer is queued in internal structure on DSP */
FALSE, /* DGCHNLXFERSTART : DSP->GPP CHNL Transfer -
Initiating a buffer transfer by DSP */
FALSE, /* DGCHNLXFERPROCESS : DSP->GPP CHNL Transfer - Actual
transfer of buffer is going to take place */
FALSE, /* DGCHNLXFERCOMPL : DSP->GPP CHNL Transfer - Buffer
transfer is complete */
FALSE, /* DGCHNLRECLPEND : DSP->GPP CHNL Transfer - RECLAIM:
Wait on a semaphore */
FALSE, /* DGCHNLRECLPOST : DSP->GPP CHNL Transfer - RECLAIM:
Posting the Semaphore */
10, /* MSGIDRANGESTART : MSG ID range: lower limit */
20 /* MSGIDRANGEEND : MSG ID range: upper limit */
} ;
/** ============================================================================
* @name LINKCFG_linkDrvObjects
*
* @desc Array of Link driver objects in the system.
* ============================================================================
*/
STATIC LINKCFG_LinkDrv LINKCFG_linkDrvObjects [] =
{
{
"SHMDRV", /* NAME
: Name of the link driver */
DRVHANDSHAKEPOLLCOUNT, /*
HSHKPOLLCOUNT : Poll value for which handshake waits (-1 if infinite) */
(Uint32) SHAREDENTRYID1, /* MEMENTRY
: Memory entry ID (-1 if not needed) */
0, /* IPSTABLEID
: ID of the IPS table used */
sizeof (LINKCFG_ipsTable_00) / sizeof (LINKCFG_Ips), /* IPSENTRIES
: Number of IPS supported */
0, /*
POOLTABLEID : ID of the POOL table */
sizeof (LINKCFG_poolTable_00) / sizeof (LINKCFG_Pool), /* NUMPOOLS
: Number of POOLs supported */
0, /*
DATATABLEID : ID of the data driver table */
sizeof (LINKCFG_dataTable_00) / sizeof (LINKCFG_DataDrv), /* NUMDATADRV
: Number of data drivers supported */
0, /* MQTID
: ID of the MQT */
0, /*
RINGIOTABLEID : RingIO Table Id used for this DSP */
0, /*
MPLISTTABLEID : MpList Table Id used for this DSP */
0 /*
MPCSTABLEID : MPCS Table ID used for this DSP */
},
} ;
/** ============================================================================
* @name LINKCFG_dspObjects
*
* @desc Array of configuration objects for the DSPs in the system.
* ============================================================================
*/
STATIC LINKCFG_Dsp LINKCFG_dspObject =
{
"DM6446GEM", /* NAME
: Name of the DSP */
DspArch_C64x, /* ARCHITECTURE
: DSP architecture */
"COFF", /* LOADERNAME
: Name of the DSP executable loader */
FALSE, /* AUTOSTART
: Autostart the DSP (Not supported) */
"DEFAULT.OUT", /* EXECUTABLE
: Executable for autostart */
DSP_BootMode_Boot_Pwr, /* DOPOWERCTRL
: Link does the Power Ctrl of DSP. */
RESETCTRLADDR, /* RESUMEADDR
: Resume address */
RESETCTRLADDR, /* RESETVECTOR
: Reset Vector for the DSP */
RESETCTRLSIZE, /* RESETCODESIZE
: Size of code at DSP Reset Vector */
1, /* MADUSIZE
: DSP Minimum Addressable Data Unit */
(Uint32) -1, /* CPUFREQ
: DSP Frequency (in KHz), -1 if default setting is to be used */
Endianism_Little, /* ENDIAN
: DSP Endianism */
FALSE, /* WORDSWAP
: Words must be swapped when writing to memory */
0, /* MEMTABLEID
: ID of the memory table used */
sizeof (LINKCFG_memTable_00)/sizeof (LINKCFG_MemEntry), /* MEMENTRIES
: Number of entries in memory table */
0, /* LINKDRVID
: ID of the link driver used */
0, /* ARG1
: Bus No of PCI card */
0, /* ARG2
: Slot No of PCI card */
0, /* ARG3
: DSPLINK Shared memory region for control data structures creation */
0, /* ARG4
: Unused */
(Uint32) -1l /* ARG5
: EDMA channel number, Unused for DM6446*/
} ;
/** ============================================================================
* @name DM6446GEM_SHMEM_Config
*
* @desc DSP/BIOS LINK configuration structure.
* ============================================================================
*/
LINKCFG_DspConfig DM6446GEM_SHMEM_Config = {
(LINKCFG_Dsp *) &LINKCFG_dspObject, /* DSPOBJECTS
: Array of DSP objects */
sizeof (LINKCFG_linkDrvObjects)/sizeof (LINKCFG_LinkDrv), /* NUMLINKDRVS
: Number of Link Drviers*/
(LINKCFG_LinkDrv *) LINKCFG_linkDrvObjects, /*
LINKDRVOBJECTS : Array of Link Driver objects */
sizeof (LINKCFG_memTables)/sizeof (LINKCFG_MemEntry *), /* NUMMEMTABLES
: Number of memory tables */
(LINKCFG_MemEntry **) LINKCFG_memTables, /* MEMTABLES
: Array of Memory tables */
sizeof (LINKCFG_ipsTables)/sizeof (LINKCFG_Ips *), /* NUMIPSTABLES
: Number of IPS tables */
(LINKCFG_Ips **) LINKCFG_ipsTables, /* IPSTABLES
: Array of IPS tables */
sizeof (LINKCFG_poolTables)/sizeof (LINKCFG_Pool *), /*
NUMPOOLTABLES : Number of POOL tables */
(LINKCFG_Pool **) LINKCFG_poolTables, /* POOLTABLES
: Array of Pool tables */
sizeof (LINKCFG_dataTables)/sizeof (LINKCFG_DataDrv *), /*
NUMDATATABLES : Number of data tables */
(LINKCFG_DataDrv **) LINKCFG_dataTables, /* DATATABLES
: Array of data tables */
sizeof (LINKCFG_mqtObjects)/sizeof (LINKCFG_Mqt), /* NUMMQTS
: Number of MQTs */
(LINKCFG_Mqt *) LINKCFG_mqtObjects, /* MQTOBJECTS
: Array of MQT objects */
sizeof (LINKCFG_ringIoObjects)/sizeof (LINKCFG_RingIo), /*
NUMRINGIOTABLES: Number of RINGIO tables */
(LINKCFG_RingIo *) LINKCFG_ringIoObjects, /*
RINGIOOBJECTS : Array of RINGIO objects */
sizeof (LINKCFG_mplistObjects)/sizeof (LINKCFG_MpList), /*
NUMMPLISTTABLES: Number of MPLIST tables */
(LINKCFG_MpList *) LINKCFG_mplistObjects, /*
MPLISTOBJECTS : Array of MPLIST objects */
sizeof (LINKCFG_mpcsObjects)/sizeof (LINKCFG_Mpcs), /*
NUMMPCSTABLES : Number of MPCS tables */
(LINKCFG_Mpcs *) LINKCFG_mpcsObjects, /* MPCSOBJECTS
: Array of MPCS objects */
(LINKCFG_Log *) &LINKCFG_logObject, /* LOGOBJECT
: Pointer to LOG object */
} ;
#if defined (__cplusplus)
}
#endif /* defined (__cplusplus) */
/** ============================================================================
* @file dsplink-dm6446gem-base.tci
*
* @path $(DSPLINK)/dsp/inc/DspBios/5.XX/DM6446GEM/
*
* @desc This file defines base configuration for DSP/BIOS LINK.
*
* @ver 1.61.03
* ============================================================================
* Copyright (c) Texas Instruments Incorporated 2002-2008
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied or provided.
* ============================================================================
*/
/* ============================================================================
* Load assert support
* ============================================================================
*/
utils.importFile("assert.tci");
/* ============================================================================
* Load base TCI file.
* ============================================================================
*/
utils.loadPlatform("ti.platforms.evmDM6446");
/* ============================================================================
* Enable common BIOS features used by all examples
* ============================================================================
*/
bios.disableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.disableRtdx(prog);
bios.enableTskManager(prog);
/* ============================================================================
* GBL
* ============================================================================
*/
prog.module("GBL").ENABLEALLTRC = false ;
prog.module("GBL").PROCID = parseInt (arguments [0]) ;
prog.module("GBL").C64PLUSCONFIGURE = true ;
prog.module("GBL").C64PLUSL2CFG = "32k" ;
prog.module("GBL").C64PLUSL1DCFG = "32k" ;
prog.module("GBL").C64PLUSMAR128to159 = 0x00008000 ;
/* ============================================================================
* MEM
* ============================================================================
*/
prog.module("MEM").STACKSIZE = 0x1000 ;
/* ============================================================================
* MEM : RESET_VECTOR
* ============================================================================
*/
var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR");
RESET_VECTOR.base = 0x8FF00000;
RESET_VECTOR.len = 0x00000080;
RESET_VECTOR.space = "code/data";
RESET_VECTOR.createHeap = false;
RESET_VECTOR.comment = "RESET_VECTOR";
/* ============================================================================
* MEM : DDR2
* ============================================================================
*/
var DDR2 = prog.module("MEM").instance("DDR2");
DDR2.base = 0x8FF00080;
DDR2.len = 0x000FFF80;
DDR2.space = "code/data";
DDR2.createHeap = true;
DDR2.heapSize = 0x10000;
DDR2.comment = "DDR2";
/* ============================================================================
* MEM : DSPLINKMEM
* ============================================================================
*/
var DSPLINKMEM = prog.module("MEM").create("DSPLINKMEM");
DSPLINKMEM.base = 0x8FE00000;
DSPLINKMEM.len = 0x00030000;
DSPLINKMEM.createHeap = false;
DSPLINKMEM.comment = "DSPLINKMEM";
/* ============================================================================
* MEM : POOLMEM
* ============================================================================
*/
var POOLMEM = prog.module("MEM").create("POOLMEM");
POOLMEM.base = 0x8FE30000;
POOLMEM.len = 0x000D0000;
POOLMEM.createHeap = false;
POOLMEM.comment = "POOLMEM";
/* ============================================================================
* MEM : IRAM
* ============================================================================
*/
var IRAM = prog.module("MEM").instance("IRAM");
IRAM.len = 0x8000 ;
/* ===========================================================================
* Editing the mem_ext structure to set the external memory setting for your
* board. For more information see section 4.2 in spru007 pdf.
* ===========================================================================
*/
var mem_ext = [
{
comment: "DDRALGHEAP: off-chip memory for dynamic algmem allocation",
name: "DDRALGHEAP",
base: 0x88000000,
len: 0x04000000,
space: "code/data"
},
{
comment: "L1DSRAM: off-chip memory for dynamic algmem allocation",
name: "L1DSRAM",
base: 0x11F04000,
len: 0x10000,
space: "data"
},
{
comment: "L1PSRAM: on chip memory for program",
name: "L1PSRAM",
base: 0x11e08000,
len: 0x4000,
space: "data"
},
{
comment: "DDR2: off-chip memory for code and data",
name: "DDR2",
base: 0x8FA00000,
len: 0x00400000,
space: "code/data"
},
{
comment: "DSPLINK: off-chip memory for DSPLINK code and data",
name: "DSPLINKMEM",
base: 0x8FE00000,
len: 0x00030000,
space: "code/data"
},
{
comment: "POOLMEM: memory used for pools",
name: "POOLMEM",
base: 0x8FE30000,
len: 0x000D0000,
space: "code/data"
},
{
comment: "RESET_VECTOR: off-chip memory for the reset vector table",
name: "RESET_VECTOR",
base: 0x8FF00000,
len: 0x00000080,
space: "code/data"
},
];
/* ===========================================================================
* Editing the Param structure to match the CPU setting for your board.
* For more information see section 4.3 "Setting Platform Param" in spru007
pdf.
* ===========================================================================
*/
var params = {
clockRate: 594,
catalogName: "ti.catalog.c6000",
deviceName: "DM6446",
mem: mem_ext
};
/* ===========================================================================
* Customize generic platform file with parameters specified above.
* This loads the specified platform configuration with minimal set of DSP /
* BIOS components. We explicitly enable the components required furthur.
* For futhur refrence one can look into section 3.3 of spru007 pdf.
* ===========================================================================
*/
utils.loadPlatform("ti.platforms.generic", params);
/* ===========================================================================
* Enable heaps for the memory section created in mem_ext structure and enable
* task manager.
* ===========================================================================
*/
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);
/* ===========================================================================
* Create heaps in memory segments that are to have heap
* ===========================================================================
*/
bios.DDR2.createHeap = true;
bios.DDR2.heapSize = 0x10000;
bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len;
/* ===========================================================================
* Enable heaps in the L1DSRAM (internal L1 cache ram, fixed size)
* and define the label for heap usage. We are setting the value of
* bios.L1DSRAM.len again to 64 K because loadPlatform function call by,default
* assumes the value of L1DSRAM Cache to be 32 K and resets the length of
* L1DSRAM to 48 K.
* ===========================================================================
*/
bios.L1DSRAM.createHeap = true;
bios.L1DSRAM.len = 0x10000;
bios.L1DSRAM.heapSize = bios.L1DSRAM.len;
bios.L1DSRAM.enableHeapLabel = true;
bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP");
/* ===========================================================================
* GBL
* ===========================================================================
*/
/* ===========================================================================
* Settings corresponding to GBL Module can be reffered to Section 2.8 in PDF
* spru403. This is required to set the memory configuration in TCF File.
* ===========================================================================
*/
prog.module("GBL").C64PLUSCONFIGURE = true ;
prog.module("GBL").C64PLUSL2CFG = "64k" ;
prog.module("GBL").C64PLUSL1DCFG = "16k" ;
prog.module("GBL").C64PLUSL1PCFG = "16k" ;
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ff80;
/* ===========================================================================
* MEM
* ===========================================================================
*/
/* ===========================================================================
* The size of the global stack in Minimum Addressable Data Units. It is
* the estimated minimum global stack size required for this application.
* For furthur details one can refer to CCS help.
* ===========================================================================
*/
prog.module("MEM").STACKSIZE = 0x1000 ;
/* ===========================================================================
* This defines the size of the .args section. The .args section contains the
* argc, argv, and envp arguments to the program's main() function. Code
* Composer loads arguments for the main() function into the .args section.
* The .args section is parsed by the boot file.
* For furthur details one can refer to CCS help.
* ===========================================================================
*/
prog.module("MEM").ARGSSIZE = 200;
/* ===========================================================================
* Enable MSGQ and POOL Managers
* ===========================================================================
*/
/* ===========================================================================
* The MSGQ and POOL module allows for the structured sending and receiving
* of variable length messages. This module can be used for homogeneous or
* heterogeneous multi-processor messaging.
* For furthur details one can refer to CCS help.
* ===========================================================================
*/
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;
/* ===========================================================================
* Set all code and data sections to use DDR2
* ===========================================================================
*/
/* ===========================================================================
* One should change all the BIOS section to DDR2 / DDRALGHEAP so as to improve
* the perfomance by utlizing Internal mmemory for Code/ Data placement.
* ===========================================================================
*/
bios.setMemCodeSections (prog, bios.DDR2) ;
bios.setMemDataNoHeapSections (prog, bios.DDR2) ;
bios.setMemDataHeapSections (prog, bios.DDRALGHEAP) ;
/* ===========================================================================
* Since all the sections are pointing to DDR2 / DDRALGHEAP we can remove the
* IRAM section which is created as default and will not be furthur used.
* ===========================================================================
*/
bios.MEM.instance("IRAM").destroy();
/* ===========================================================================
* MEM : Global
* ===========================================================================
*/
/* ===========================================================================
* One should change all the BIOS section to DDR2 / DDRALGHEAP so as to improve
* the perfomance by utlizing Internal mmemory for Code/ Data placement.
* ===========================================================================
*/
prog.module("MEM").BIOSOBJSEG = bios.DDRALGHEAP;
prog.module("MEM").MALLOCSEG = bios.DDRALGHEAP;
/* ===========================================================================
* TSK : Global
* ===========================================================================
*/
/* ===========================================================================
* One should change all the BIOS section to DDR2 / DDRALGHEAP so as to improve
* the perfomance by utlizing Internal mmemory for Code/ Data placement.
* ===========================================================================
*/
prog.module("TSK").STACKSEG = bios.DDRALGHEAP ;
/* ===========================================================================
* Generate configuration files...
* ===========================================================================
*/
if (config.hasReportedError == false) {
prog.gen();
}
/*****************************************************************************/
/* */
/* ITTIAM SYSTEMS PVT LTD, BANGALORE */
/* COPYRIGHT(C) 2008 */
/* */
/* This program is proprietary to Ittiam Systems Pvt. Ltd. and is protected */
/* under Indian Copyright Act as an unpublished work.Its use and disclosure */
/* is limited by the terms and conditions of a license agreement. It may */
/* be copied or otherwise reproduced or disclosed to persons outside the */
/* licensee 's organization except in accordance with the terms and */
/* conditions of such an agreement. All copies and reproductions shall be */
/* the property of Ittiam Systems Pvt. Ltd. and must bear this notice */
/* in its entirety. */
/* */
/*****************************************************************************/
/*
* ======== mpeg2_dec_app.cfg ========
*/
environment['xdc.cfg.check.fatal'] = 'false';
/* use the tracing utility module */
var TraceUtil = xdc.useModule('ti.sdo.ce.utils.trace.TraceUtil');
TraceUtil.attrs = TraceUtil.SOCRATES_TRACING;
/* set up OSAL */
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_LINUX;
osalGlobal.armDspLinkConfig = {
memTable: [
["DDRALGHEAP", {addr: 0x88000000, size: 0x04000000, type:
"other"}],
["RESET_VECTOR", {addr: 0x8F00000, size: 0x00000080, type:
"reset"}],
["DDR2", {addr: 0x8FF00080, size: 0x000FFF80, type: "main"}],
["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00030000, type:
"link"}],
],
};
/*
* ======== Engine Configuration ========
*/
var Engine = xdc.useModule('ti.sdo.ce.Engine');
var myEngine = Engine.createFromServer(
"mpeg2_dec_server", // Engine name (as referred to in the C app)
"./server_production/mpeg2_dec_server.x64P", // path to server exe,
relative to its package dir
"ittiam.servers.mpeg2_dec_server" // server package
);
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