Hi Steve, I have attached the files with the mail.
Below is the link where I took the patch from. http://www.mail-archive.com/[email protected]/msg04407.html Thanks, azam. On Thu, Jul 9, 2009 at 4:46 PM, Steve Chen <[email protected]> wrote: > On Thu, 2009-07-09 at 10:22 +0530, Azam Ansari wrote: > > Hi Steve, > > > > I added the patch for Power Management in DM355. But during > > compilation I get following error: > > > > arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in > > initializer > > arch/arm/mach-davinci/io.c:47: warning: implicit declaration of > > function `phys_to_pfn' > > arch/arm/mach-davinci/io.c:47: error: initializer element is not > > constant > > arch/arm/mach-davinci/io.c:47: error: (near initialization for > > `davinci_io_desc[1].physical') > > arch/arm/mach-davinci/io.c:50: error: initializer element is not > > constant > > arch/arm/mach-davinci/io.c:50: error: (near initialization for > > `davinci_io_desc[1]') > > arch/arm/mach-davinci/io.c:53: error: unknown field `pfn' specified in > > initializer > > arch/arm/mach-davinci/io.c:53: error: initializer element is not > > constant > > arch/arm/mach-davinci/io.c:53: error: (near initialization for > > `davinci_io_desc[2].physical') > > arch/arm/mach-davinci/io.c:56: error: initializer element is not > > constant > > arch/arm/mach-davinci/io.c:56: error: (near initialization for > > `davinci_io_desc[2]') > > arch/arm/mach-davinci/io.c: In function `davinci_map_common_io': > > arch/arm/mach-davinci/io.c: > > 111: warning: too few arguments for format > > Kind of difficult to tell without having the source code available. > > > > > > So bypass this error I commented following lines in > > arch/arm/mach-davinci/io.c file: > > .pfn = phys_to_pfn(DDR2_CTRL_PHYS), > > .pfn = phys_to_pfn(TCM_PHYS), > > > > > > But then I get following error during linking. > > > > > > arch/arm/mach-davinci/built-in.o(.text+0x4fd4): In function > > `davinci_pm_idle': > > arch/arm/mach-davinci/sleep.S: undefined reference to > > `timer_dyn_reprogram' > > arch/arm/mach-davinci/built-in.o(.text > > +0x5004):arch/arm/mach-davinci/sleep.S: undefined reference to > > `timer_dyn_reprogram' > > arch/arm/mach-davinci/built-in.o(.init.text+0x14cc): In function > > `davinci_pm_init': > > arch/arm/mach-davinci/sleep.S: undefined reference to > > `suspend_set_ops' > > > > > > I didn't find suspend_set_ops() and timer_dyn_reprogram() functions > > defined in the kernel source tree. > > > > Please let me know where will I find the following function > > definition? > > > > Also how do I correct the compilation error that I am getting in io.c > > file? > > I don't know. If you share the patch, I can look at it and perhaps come > up with a few suggestions. > > Regards, > > Steve > >
/*
* linux/arch/arm/mach-davinci/pm.c
*
* DaVinci Power Management Routines
*
* Copyright 2008 Dirk Behme <[EMAIL PROTECTED]>
*
* Based on arch/arm/mach-omap2/pm.c from:
*
* Copyright (C) 2005 Texas Instruments, Inc.
* Copyright (C) 2006 Nokia Corporation
*
* Written by:
* Richard Woodruff <[EMAIL PROTECTED]>
* Tony Lindgren
* Juha Yrjola
* Amit Kucheria <[EMAIL PROTECTED]>
* Igor Stoppa <[EMAIL PROTECTED]>
*
* Based on pm.c for omap1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/suspend.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/arch/edma.h>
#include <asm/arch/tcm.h>
#include <asm/arch/pm.h>
static void (*davinci_tcm_idle)(void);
static void (*davinci_tcm_suspend)(void);
static void (*saved_idle)(void);
static unsigned short enable_standby;
static unsigned int count_idle;
static unsigned int count_standby;
static ssize_t davinci_pm_idle_show(struct kset *subsys, char *buf)
{
return sprintf(buf, "%hu\n", count_idle);
}
static struct subsys_attribute idle_attr = {
.attr = {
.name = __stringify(count_idle),
.mode = 0644,
},
.show = davinci_pm_idle_show,
};
static ssize_t davinci_pm_standby_show(struct kset *subsys, char *buf)
{
return sprintf(buf, "%hu\n", count_standby);
}
static struct subsys_attribute standby_attr = {
.attr = {
.name = __stringify(count_standby),
.mode = 0644,
},
.show = davinci_pm_standby_show,
};
static int davinci_irq_pending(void)
{
u32 pending, enabled0, enabled1;
enabled0 = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
enabled1 = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
/* Any enabled FIQ0 pending? */
pending = davinci_irq_readl(FIQ_REG0_OFFSET);
if (~pending & enabled0)
return 1;
/* Any enabled FIQ1 pending? */
pending = davinci_irq_readl(FIQ_REG1_OFFSET);
if (~pending & enabled1)
return 1;
/* Any enabled IRQ0 pending? */
pending = davinci_irq_readl(IRQ_REG0_OFFSET);
if (~pending & enabled0)
return 1;
/* Any enabled IRQ1 pending? */
pending = davinci_irq_readl(IRQ_REG1_OFFSET);
if (~pending & enabled1)
return 1;
return 0;
}
static void davinci_enter_standby(void)
{
u32 enabled0, enabled1;
/* ToDo: Disable all unused peripherals using PSC */
/* Save irq enable masks */
enabled0 = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
enabled1 = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
/* Configure wake interrupts. Disable all interrupts
* except wake irqs */
davinci_irq_writel(1 << IRQ_EMACINT, IRQ_ENT_REG0_OFFSET);
davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (davinci_irq_pending())
goto no_sleep;
/* Jump to suspend code in TCM */
davinci_tcm_suspend();
count_standby++;
enable_standby = 0;
no_sleep:
/* Reenable interrupts, rewrite saved enable configuration */
davinci_irq_writel(enabled0, IRQ_ENT_REG0_OFFSET);
davinci_irq_writel(enabled1, IRQ_ENT_REG1_OFFSET);
}
static void davinci_enter_idle(void)
{
/* Jump to idle code in TCM */
davinci_tcm_idle();
count_idle++;
}
static int davinci_can_sleep(void)
{
if (!enable_standby)
return 0;
if (davinci_dma_running())
return 0;
return 1;
}
static void davinci_pm_idle(void)
{
local_irq_disable();
local_fiq_disable();
if (!davinci_can_sleep()) {
/* timer_dyn_reprogram() takes about 100-200 us to complete */
timer_dyn_reprogram();
if (davinci_irq_pending())
goto out;
davinci_enter_idle();
goto out;
}
/*
* Since an interrupt may set up a timer, we don't want to
* reprogram the hardware timer with interrupts enabled.
* Re-enable interrupts only after returning from idle.
*/
timer_dyn_reprogram();
if (davinci_irq_pending())
goto out;
davinci_enter_standby();
out:
local_fiq_enable();
local_irq_enable();
}
static int davinci_pm_prepare(void)
{
/* We cannot sleep in idle until we have resumed */
saved_idle = pm_idle;
pm_idle = NULL;
return 0;
}
static int davinci_pm_enter(suspend_state_t state)
{
int ret = 0;
switch (state) {
case PM_SUSPEND_STANDBY:
enable_standby = 1;
davinci_pm_idle();
break;
case PM_SUSPEND_MEM:
break;
default:
ret = -EINVAL;
}
return ret;
}
static void davinci_pm_finish(void)
{
pm_idle = saved_idle;
}
static int davinci_pm_valid_standby(suspend_state_t state)
{
return state == PM_SUSPEND_STANDBY;
}
static struct platform_suspend_ops davinci_pm_ops = {
.prepare = davinci_pm_prepare,
.enter = davinci_pm_enter,
.finish = davinci_pm_finish,
.valid = davinci_pm_valid_standby,
};
int __init davinci_pm_init(void)
{
u32 tmp;
printk(KERN_INFO "Power Management for DaVinci initializing\n");
/* Check if TCM is mapped using one 1MB desc, avoid MMU walks while
* running from TCM */
/* Get TTB from TTBR */
asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (tmp) :);
/* Convert TTB to virtual address */
tmp = (u32)phys_to_virt(tmp & 0xFFFFC000);
/* Get table entry */
tmp = *(u32 *) (tmp + (TCM_VIRT >> 18));
/* Section bits set ? */
if ((tmp & 0x3) != 0x2) {
printk(KERN_ERR "TCM not mapped using section descriptor: " \
"0x%08x\n", tmp);
return -EFAULT;
}
/*
* We copy the assembler sleep/wakeup routines to ITCM.
* These routines need to be in ITCM as that's the only
* memory the ARM can see when it wakes up if we switch
* main memory (SDRAM) to self refresh.
*/
davinci_tcm_idle = davinci_tcm_push(davinci_idle_loop_suspend,
davinci_idle_loop_suspend_sz);
davinci_tcm_suspend = davinci_tcm_push(davinci_cpu_suspend,
davinci_cpu_suspend_sz);
suspend_set_ops(&davinci_pm_ops);
pm_idle = davinci_pm_idle;
tmp = subsys_create_file(&power_subsys, &idle_attr);
if (tmp)
printk(KERN_ERR "subsys_create_file idle_count failed: %d\n",
tmp);
tmp = subsys_create_file(&power_subsys, &standby_attr);
if (tmp)
printk(KERN_ERR "subsys_create_file standby_count failed: %d\n",
tmp);
return 0;
}
late_initcall(davinci_pm_init);
/*
* linux/arch/arm/mach-davinci/tcm.c
*
* DaVinci interal TCM detection and management
*
* Copyright 2007 Dirk Behme <[EMAIL PROTECTED]>
*
* Based on arch/arm/plat-omap/sram.c from:
*
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <[EMAIL PROTECTED]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm-arm/arch/io.h>
#include <asm/arch/tcm.h>
static unsigned long davinci_itcm_base;
static unsigned long davinci_itcm_size;
static unsigned long davinci_itcm_ceil;
#define ROUND_DOWN(value, boundary) ((value) & (~((boundary)-1)))
void *davinci_tcm_push(void *start, unsigned long size)
{
if ((size > davinci_itcm_ceil) || (davinci_itcm_size == 0)) {
printk(KERN_ERR "Not enough space in ITCM\n");
return NULL;
}
davinci_itcm_ceil -= size;
davinci_itcm_ceil = ROUND_DOWN(davinci_itcm_ceil, sizeof(void *));
memcpy((void *)davinci_itcm_ceil, start, size);
return (void *)davinci_itcm_ceil;
}
void __init davinci_init_tcm(void)
{
u32 tmp;
davinci_itcm_size = 0;
/* Check for ITCM */
asm volatile ("mrc p15, 0, %0, c0, c0, 2" : "=r" (tmp) :);
if (!(tmp & 0x1)) {
printk(KERN_ERR "No ITCM found\n");
return;
}
/* Check for ITCM size */
asm volatile ("mrc p15, 0, %0, c9, c1, 1" : "=r" (tmp) :);
/* Wonder: Manual states that ITCM is 16k, i.e. 0x5
* should be returned? */
if (((tmp >> 2) & 0xF) != 0x6) {
printk(KERN_ERR "Wrong ITCM size. Not 32k? " \
"ITCM region reg: 0x%08x\n", tmp);
return;
}
/* Everything looks okay, enable ITCM */
tmp = (TCM_PHYS << 12) | 1;
asm volatile ("mcr p15, 0, %0, c9, c1, 1" : : "r" (tmp));
davinci_itcm_base = TCM_VIRT;
davinci_itcm_size = SZ_16K;
davinci_itcm_ceil = davinci_itcm_base + davinci_itcm_size;
}
sleep.S
Description: Binary data
/* * linux/include/asm-arm/arch-davinci/tcm.h * * Interface for functions that need to be run in internal TCM * * Copyright 2007 Dirk Behme <[EMAIL PROTECTED]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ARCH_ARM_DAVINCI_TCM_H #define __ARCH_ARM_DAVINCI_TCM_H extern void *davinci_tcm_push(void *start, unsigned long size); extern void davinci_init_tcm(void); #endif /* __ARCH_ARM_DAVINCI_TCM_H */
/*
* linux/include/asm-arm/arch-davinci/io.h
*
* Copyright (C) 2006 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/arch/hardware.h>
#include <asm/types.h>
#include <asm/hardware.h>
#define TCM_PHYS DAVINCI_TCM_BASE /* 0x00000000 */
#define TCM_VIRT 0xfea00000
#define TCM_SIZE SZ_1M /* use a section desc */
#define DDR2_CTRL_PHYS DAVINCI_DDR2_CTRL_BASE /* 0x20000000 */
#define DDR2_CTRL_VIRT 0xfeb00000
#define DDR2_CTRL_SIZE SZ_1M
#define IO_SPACE_LIMIT 0xffffffff
/*
* ----------------------------------------------------------------------------
* I/O mapping
* ----------------------------------------------------------------------------
*/
#define IO_PHYS 0x01c00000
#define IO_VIRT 0xe1000000
#define IO_SIZE SZ_4M
/* DM646X need to map 0x02000000-0x02400000 to 0x01e400000-0x0e1800000*/
/* This is put in the generic section so IRAM is mapped the same between
DaVinci and DM646X - Note that this will leave a hole for DaVinci */
#define DM646X_IO_PHYS 0x02000000
#define DM646X_IO_VIRT (IO_VIRT + IO_SIZE)
#define DM646X_IO_SIZE SZ_4M
#define DAVINCI_IRAM_VIRT (DM646X_IO_VIRT + DM646X_IO_SIZE)
/* after 4M of IO space */
#define DAVINCI_IRAM_SIZE SZ_16K
/*
* DM644X specific mappings
*/
/* DaVinci IRAM mapping */
#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM (Data) */
/* handle VLYNQ remap */
#define VLYNQ_REMOTE_PHYS 0x0C000000
#define VLYNQ_REMOTE_VIRT DAVINCI_IRAM_VIRT + DAVINCI_IRAM_SIZE
#define VLYNQ_REMOTE_SIZE SZ_64M
#define VLYNQ_PHYS_TO_VIRT(addr) ((addr) - (VLYNQ_REMOTE_PHYS) + \
(VLYNQ_REMOTE_VIRT))
#define VLYNQ_VIRT_TO_PHYS(addr) ((addr) + (VLYNQ_REMOTE_PHYS) - \
(VLYNQ_REMOTE_VIRT))
/*
* DM646X specific mappings
*/
/* IRAM mappings */
#define DM646X_IRAM_BASE 0x00010000 /* ARM Internal RAM (Data) */
/* handle DM646X EMIF remap */
#define EMIF_CNTRL_VIRT (DAVINCI_IRAM_VIRT + DAVINCI_IRAM_SIZE)
#define EMIF_P2V(addr) ((emifregsovly) \
((addr) - (DAVINCI_DM646X_ASYNC_EMIF_CNTRL_BASE) + (EMIF_CNTRL_VIRT)))
/*
* cconversion functions
*/
#define io_p2v(pa) (((pa) - (IO_PHYS)) + IO_VIRT)
#define io_v2p(va) (((va) - (IO_VIRT)) + IO_PHYS)
#define IO_ADDRESS(x) io_p2v(x)
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define PCIO_BASE 0
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#ifndef __ASSEMBLER__
/*
* Functions to access the DaVinci IO region
*
* NOTE: - Use davinci_read/write[bwl] for physical register addresses
* - Use __raw_read/write[bwl]() for virtual register addresses
* - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
* - DO NOT use hardcoded virtual addresses to allow changing the
* IO address space again if needed
*/
#define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a))
#define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a))
#define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a))
#define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v))
#define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
#define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
/* 16 bit uses LDRH/STRH, base +/- offset_8 */
typedef struct { volatile u16 offset[256]; } __regbase16;
#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
->offset[((vaddr)&0xff)>>1]
#define __REG16(paddr) __REGV16(io_p2v(paddr))
/* 8/32 bit uses LDR/STR, base +/- offset_12 */
typedef struct { volatile u8 offset[4096]; } __regbase8;
#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
->offset[((vaddr)&4095)>>0]
#define __REG8(paddr) __REGV8(io_p2v(paddr))
typedef struct { volatile u32 offset[4096]; } __regbase32;
#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
->offset[((vaddr)&4095)>>2]
/* FIXME: Just for compilation sake changed from __REG32 to __REG */
#define __REG(paddr) __REGV32(io_p2v(paddr))
extern void davinci_map_common_io(void);
extern void davinci_init_common_hw(void);
#else
#define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
#endif
#endif /* __ASM_ARCH_IO_H */
/* * linux/include/asm-arm/arch-davinci/pm.h * * Header file for DaVinci Power Management Routines * * Copyright 2007 Dirk Behme <[EMAIL PROTECTED]> * * Based on linux/include/asm-arm/arch-omap/pm.h from: * * Author: MontaVista Software, Inc. * [EMAIL PROTECTED] * * Copyright 2002 MontaVista Software Inc. * * Cleanup 2004 for Linux 2.6 by Dirk Behme <[EMAIL PROTECTED]> * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __ASM_ARCH_DAVINCI_PM_H #define __ASM_ARCH_DAVINCI_PM_H #ifndef __ASSEMBLER__ extern void davinci_cpu_suspend(void); extern void davinci_idle_loop_suspend(void); extern unsigned int davinci_cpu_suspend_sz; extern unsigned int davinci_idle_loop_suspend_sz; extern struct kset power_subsys; #endif /* ASSEMBLER */ #endif /* __ASM_ARCH_DAVINCI_PM_H */
/* * linux/include/asm-arm/arch-davinci/hardware.h * * Copyright (C) 2006 Texas Instruments. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. * */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H /************************************************************************** * Included Files **************************************************************************/ #include <linux/config.h> #include <asm/sizes.h> #include <asm/memory.h> #include <asm/arch/io.h> /* * DaVinci (DM644X) Base register addresses */ #define DAVINCI_TCM_BASE (0x00000000) #define DAVINCI_ROM_BASE (0x00004000) #define DAVINCI_DMA_3PCC_BASE (0x01C00000) #define DAVINCI_DMA_3PTC0_BASE (0x01C10000) #define DAVINCI_DMA_3PTC1_BASE (0x01C10400) #define DAVINCI_UART0_BASE (0x01C20000) #define DAVINCI_UART1_BASE (0x01C20400) #define DAVINCI_I2C_BASE (0x01C21000) #define DAVINCI_TIMER0_BASE (0x01C21400) #define DAVINCI_TIMER1_BASE (0x01C21800) #define DAVINCI_WDOG_BASE (0x01C21C00) #define DAVINCI_PWM0_BASE (0x01C22000) #define DAVINCI_PWM1_BASE (0x01C22400) #define DAVINCI_PWM2_BASE (0x01C22800) #define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) #define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) #define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) #define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) #define DAVINCI_ARM_INTC_BASE (0x01C48000) #define DAVINCI_IEEE1394_BASE (0x01C60000) #define DAVINCI_USB_OTG_BASE (0x01C64000) #define DAVINCI_CFC_ATA_BASE (0x01C66000) #define DAVINCI_SPI_BASE (0x01C66800) #define DAVINCI_GPIO_BASE (0x01C67000) #define DAVINCI_UHPI_BASE (0x01C67800) #define DAVINCI_VPSS_REGS_BASE (0x01C70000) #define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) #define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) #define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) #define DAVINCI_IMCOP_BASE (0x01CC0000) #define DAVINCI_VLYNQ_BASE (0x01E01000) #define DAVINCI_MCBSP_BASE (0x01E02000) #define DAVINCI_MCBSP_RX_DMA_PORT DAVINCI_MCBSP_BASE #define DAVINCI_MCBSP_TX_DMA_PORT (DAVINCI_MCBSP_BASE + 4) #define DAVINCI_MCBSP0_BASE DAVINCI_MCBSP_BASE #define DAVINCI_MCBSP1_BASE (0x01E04000) #define DAVINCI_MMC_SD_BASE (0x01E10000) #define DAVINCI_MS_BASE (0x01E20000) #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) #define DAVINCI_DDR2_CTRL_BASE (0x20000000) #define DM644X_ASYNC_EMIF_CNTRL_BASE (0x01E00000) #define DM644X_UART2_BASE (0x01C20800) #define DM644X_DDR2_CNTL_BASE (0x20000000) #define DM355_MMC1_BASE (0x01E00000) #define DM355_UART2_BASE (0x01E06000) #define DM355_ASYNC_EMIF_CNTRL_BASE (0x01E10000) #define DM355_MMC0_BASE (0x01E11000) /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 /* * System module registers */ #define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) #define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) /* dm355 only */ #define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) #define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) #define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) /* * LPSC Assignments */ #define DAVINCI_LPSC_VPSSMSTR 0 /* VPSS Master LPSC */ #define DAVINCI_LPSC_VPSSSLV 1 /* VPSS Slave LPSC */ #define DAVINCI_LPSC_TPCC 2 /* TPCC LPSC */ #define DAVINCI_LPSC_TPTC0 3 /* TPTC0 LPSC */ #define DAVINCI_LPSC_TPTC1 4 /* TPTC1 LPSC */ #define DAVINCI_LPSC_EMAC 5 /* EMAC LPSC */ #define DAVINCI_LPSC_EMAC_WRAPPER 6 /* EMAC WRAPPER LPSC */ #define DAVINCI_LPSC_MDIO 7 /* MDIO LPSC */ #define DAVINCI_LPSC_MMC_SD1 7 #define DAVINCI_LPSC_IEEE1394 8 /* IEEE1394 LPSC */ #define DAVINCI_LPSC_McBSP1 8 /* McBSP1 LPSC */ #define DAVINCI_LPSC_USB 9 /* USB LPSC */ #define DAVINCI_LPSC_ATA 10 /* ATA LPSC */ #define DAVINCI_LPSC_PWM3 10 /* PWM3 LPSC */ #define DAVINCI_LPSC_VLYNQ 11 /* VLYNQ LPSC */ #define DAVINCI_LPSC_UHPI 12 /* UHPI LPSC */ #define DAVINCI_LPSC_DDR_EMIF 13 /* DDR_EMIF LPSC */ #define DAVINCI_LPSC_AEMIF 14 /* AEMIF LPSC */ #define DAVINCI_LPSC_MMC_SD0 15 /* MMC_SD0 LPSC */ #define DAVINCI_LPSC_MEMSTICK 16 /* MEMSTICK LPSC */ #define DAVINCI_LPSC_McBSP0 17 /* McBSP0 LPSC */ #define DAVINCI_LPSC_I2C 18 /* I2C LPSC */ #define DAVINCI_LPSC_UART0 19 /* UART0 LPSC */ #define DAVINCI_LPSC_UART1 20 /* UART1 LPSC */ #define DAVINCI_LPSC_UART2 21 /* UART2 LPSC */ #define DAVINCI_LPSC_SPI 22 /* SPI LPSC */ #define DAVINCI_LPSC_PWM0 23 /* PWM0 LPSC */ #define DAVINCI_LPSC_PWM1 24 /* PWM1 LPSC */ #define DAVINCI_LPSC_PWM2 25 /* PWM2 LPSC */ #define DAVINCI_LPSC_GPIO 26 /* GPIO LPSC */ #define DAVINCI_LPSC_TIMER0 27 /* TIMER0 LPSC */ #define DAVINCI_LPSC_TIMER1 28 /* TIMER1 LPSC */ #define DAVINCI_LPSC_TIMER2 29 /* TIMER2 LPSC */ #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 /* SYSTEM SUBSYSTEM LPSC */ #define DAVINCI_LPSC_ARM 31 /* ARM LPSC */ #define DAVINCI_LPSC_SCR2 32 /* SCR2 LPSC */ #define DAVINCI_LPSC_SCR3 33 /* SCR3 LPSC */ #define DAVINCI_LPSC_SCR4 34 /* SCR4 LPSC */ #define DAVINCI_LPSC_CROSSBAR 35 /* CROSSBAR LPSC */ #define DAVINCI_LPSC_CFG27 36 /* CFG27 LPSC */ #define DAVINCI_LPSC_CFG3 37 /* CFG3 LPSC */ #define DAVINCI_LPSC_CFG5 38 /* CFG5 LPSC */ #define DAVINCI_LPSC_GEM 39 /* GEM LPSC */ #define DAVINCI_LPSC_IMCOP 40 /* IMCOP LPSC */ /* * DM6467 base register addresses different from origina DaVinci */ #define DAVINCI_DM646X_DMA_3PTC2_BASE (0x01C10800) #define DAVINCI_DM646X_DMA_3PTC3_BASE (0x01C10C00) #define DAVINCI_DM646X_VIDEO_PORT_BASE (0x01C12000) #define DAVINCI_DM646X_VDCE_BASE (0x01C12800) #define DAVINCI_DM646X_TSIF0_BASE (0x01C13000) #define DAVINCI_DM646X_TSIF1_BASE (0x01C13400) #define DAVINCI_DM646X_PCI_CTL_BASE (0x01C1A000) #define DAVINCI_DM646X_CRGEN0_BASE (0x01C26000) #define DAVINCI_DM646X_CRGEN1_BASE (0x01C26400) #define DAVINCI_DM646X_SEC_CONTROLLER_BASE (0x01C40400) #define DAVINCI_DM646X_MCASP0_REG_BASE (0x01D01000) #define DAVINCI_DM646X_MCASP0_DATA_PORT_BASE (0x01D01400) #define DAVINCI_DM646X_MCASP1_REG_BASE (0x01D01800) #define DAVINCI_DM646X_MCASP1_DATA_PORT_BASE (0x01D01C00) #define DAVINCI_DM646X_HDVICP0_BASE (0x02000000) #define DAVINCI_DM646X_HDVICP1_BASE (0x02200000) #define DAVINCI_DM646X_ASYNC_EMIF_CNTRL_BASE (0x20008000) #define DAVINCI_DM646X_VLYNQ_BASE (0x20010000) #define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE0_BASE (0x42000000) #define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE1_BASE (0x44000000) #define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE2_BASE (0x46000000) #define DAVINCI_DM646X_ASYNC_EMIF_DATA_CE3_BASE (0x48000000) #define DAVINCI_DM646X_VLYNQ_REMOTE_BASE (0x4C000000) /* * LPSC Assignments */ #define DAVINCI_DM646X_LPSC_RESERVED 0 /* Reserved */ #define DAVINCI_DM646X_LPSC_C64X_CPU 1 /* C64x + CPU */ #define DAVINCI_DM646X_LPSC_HDVICP0 2 /* HDVICP0 */ #define DAVINCI_DM646X_LPSC_HDVICP1 3 /* HDVICP1 */ #define DAVINCI_DM646X_LPSC_TPCC 4 /* TPCC LPSC */ #define DAVINCI_DM646X_LPSC_TPTC0 5 /* TPTC0 LPSC */ #define DAVINCI_DM646X_LPSC_TPTC1 6 /* TPTC1 LPSC */ #define DAVINCI_DM646X_LPSC_TPTC2 7 /* TPTC2 LPSC */ #define DAVINCI_DM646X_LPSC_TPTC3 8 /* TPTC3 LPSC */ #define DAVINCI_DM646X_LPSC_PCI 13 /* PCI LPSC */ #define DAVINCI_DM646X_LPSC_EMAC 14 /* EMAC LPSC */ #define DAVINCI_DM646X_LPSC_VDCE 15 /* VDCE LPSC */ #define DAVINCI_DM646X_LPSC_VPSSMSTR 16 /* VPSS Master LPSC */ #define DAVINCI_DM646X_LPSC_VPSSSLV 17 /* VPSS Slave LPSC */ #define DAVINCI_DM646X_LPSC_TSIF0 18 /* TSIF0 LPSC */ #define DAVINCI_DM646X_LPSC_TSIF1 19 /* TSIF1 LPSC */ #define DAVINCI_DM646X_LPSC_DDR_EMIF 20 /* DDR_EMIF LPSC */ #define DAVINCI_DM646X_LPSC_AEMIF 21 /* AEMIF LPSC */ #define DAVINCI_DM646X_LPSC_McASP0 22 /* McASP0 LPSC */ #define DAVINCI_DM646X_LPSC_McASP1 23 /* McASP1 LPSC */ #define DAVINCI_DM646X_LPSC_CRGEN0 24 /* CRGEN0 LPSC */ #define DAVINCI_DM646X_LPSC_CRGEN1 25 /* CRGEN1 LPSC */ #define DAVINCI_DM646X_LPSC_UART0 26 /* UART0 LPSC */ #define DAVINCI_DM646X_LPSC_UART1 27 /* UART1 LPSC */ #define DAVINCI_DM646X_LPSC_UART2 28 /* UART2 LPSC */ #define DAVINCI_DM646X_LPSC_PWM0 29 /* PWM0 LPSC */ #define DAVINCI_DM646X_LPSC_PWM1 30 /* PWM1 LPSC */ #define DAVINCI_DM646X_LPSC_I2C 31 /* I2C LPSC */ #define DAVINCI_DM646X_LPSC_SPI 32 /* SPI LPSC */ #define DAVINCI_DM646X_LPSC_GPIO 33 /* GPIO LPSC */ #define DAVINCI_DM646X_LPSC_TIMER0 34 /* TIMER0 LPSC */ #define DAVINCI_DM646X_LPSC_TIMER1 35 /* TIMER1 LPSC */ #define DAVINCI_DM646X_LPSC_ARM_INTC 45 /* ARM INTC LPSC */ /* * DM355 base register addresses different from origina DaVinci */ #define DAVINCI_DM355_TIMER2_BASE (0x01C20800) #define DAVINCI_DM355_REALTIME_BASE (0x01C20C00) #define DAVINCI_DM355_PWM3_BASE (0x01C22C00) #define DAVINCI_DM355_SPI_BASE (0x01C66000) #define DAVINCI_DM355_SPI0_BASE DAVINCI_DM355_SPI_BASE #define DAVINCI_DM355_SPI1_BASE (0x01C66800) #define DAVINCI_DM355_SPI2_BASE (0x01C67800) #define DAVINCI_DM355_VPSS_CLK_BASE DAVINCI_VPSS_REGS_BASE #define DAVINCI_DM355_VPSS_HW3A_BASE (0x01C70080) #define DAVINCI_DM355_VPSS_IPIPE0_BASE (0x01C70100) #define DAVINCI_DM355_VPSS_OSD_BASE (0x01C70200) #define DAVINCI_DM355_VPSS_HSSIF_BASE (0x01C70300) #define DAVINCI_DM355_VPSS_VENC_BASE (0x01C70400) #define DAVINCI_DM355_VPSS_CCDC_BASE (0x01C70600) #define DAVINCI_DM355_VPSS_BL_BASE (0x01C70800) #define DAVINCI_DM355_VPSS_CFA_LD_BASE (0x01C70900) #define DAVINCI_DM355_VPSS_IPIPE1_BASE (0x01C71000) #define DAVINCI_DM355_IMX_BASE (0x01CD0000) #define DAVINCI_DM355_IMX_CTL_BASE (0x01CD0380) #define DAVINCI_DM355_IMCOP_CTL_BASE (0x01CDF400) #define DAVINCI_DM355_IMCOP_SEQ_BASE (0x01CDFF00) #define DAVINCI_DM355_MMC_SD1_BASE (0x01E00000) #define DAVINCI_DM355_MCBSP0_BASE DAVINCI_MCBSP_BASE #define DAVINCI_DM355_MCBSP1_BASE (0x01E04000) #define DAVINCI_DM355_MCBSP1_RX_DMA_PORT DAVINCI_DM355_MCBSP1_BASE #define DAVINCI_DM355_MCBSP1_TX_DMA_PORT (DAVINCI_DM355_MCBSP1_BASE + 4) #define DAVINCI_DM355_UART2_BASE (0x01E06000) #define DAVINCI_DM355_ASYNC_EMIF_CNTRL_BASE (0x01E10000) #define DAVINCI_DM355_MMC_SD_BASE (0x01E11000) #define DAVINCI_DM355_MMC_SD0_BASE DAVINCI_DM355_MMC_SD_BASE #define DAVINCI_MMC_SD0_BASE DAVINCI_DM355_MMC_SD_BASE /* * Macro to access device power control */ #define DAVINCI_VDD3P3V_PWDN __REG(DAVINCI_SYSTEM_MODULE_BASE + 0x48) /* * We can have multiple VLYNQ IPs in our system. * Define 'LOW_VLYNQ_CONTROL_BASE' with the VLYNQ * IP having lowest base address. * Define 'HIGH_VLYNQ_CONTROL_BASE' with the VLYNQ * IP having highest base address. * In case of only one VLYNQ IP, define only the * 'LOW_VLYNQ_CONTROL_BASE'. */ #define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE #ifndef __ASSEMBLER__ extern void davinci_check_revision(void); #endif /* ASSEMBLER */ #endif /* __ASM_ARCH_HARDWARE_H */
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