Hi All,
I have written following function to do pll bypass.
void davinci_clk_at24MHz(void)
{
struct clk *clkp;
static struct clk *board_clks;
int count = 0, num_clks;
unsigned long pllcnt;
if (cpu_is_davinci_dm355()) {
pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLCTL);
davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt & ~BIT(0));
udelay(4);
davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, (pllcnt & ~BIT(0))
| PLLRST);
fixedrate = 24000000;
armrate = fixedrate;
commonrate = armrate / 2;
board_clks = davinci_dm355_clks;
num_clks = ARRAY_SIZE(davinci_dm355_clks);
} else if (cpu_is_davinci_dm6467()) {
fixedrate = 24000000;
div_by_four = ((PLL1_PLLM + 1) * 27000000) / 4;
div_by_six = ((PLL1_PLLM + 1) * 27000000) / 6;
div_by_eight = ((PLL1_PLLM + 1) * 27000000) / 8;
armrate = ((PLL1_PLLM + 1) * 27000000) / 2;
board_clks = davinci_dm6467_clks;
num_clks = ARRAY_SIZE(davinci_dm6467_clks);
} else {
fixedrate = 27000000;
armrate = (PLL1_PLLM + 1) * (fixedrate / 2);
commonrate = armrate / 3;
board_clks = davinci_dm644x_clks;
num_clks = ARRAY_SIZE(davinci_dm644x_clks);
}
for (clkp = board_clks; count < num_clks; count++, clkp++) {
clk_register(clkp);
/* Turn on clocks that have been enabled in the
* table above */
if (clkp->usecount) {
clk_enable(clkp);
}
}
}
I call this function through power management modules main.c file
enter_state() function.
I do following to enable PLL bypass mode.
# echo pllbypass > /sys/power/state
But I get following kernel dump after that:
Storing State to pllbypass
Unable to handle kernel paging request at virtual address df400040
pgd = c6c74000
[df400040] *pgd=00000000
Internal error: Oops: 805 [#1]
Modules linked in: dm350mmap cmemk
CPU: 0
PC is at davinci_clk_at24MHz+0x38/0x23c
LR is at enter_state+0x68/0x1cc
pc : [<c0044c8c>] lr : [<c006fea0>] Not tainted
sp : c08cbea0 ip : c08cbec8 fp : c08cbec4
r10: 0000000a r9 : c08cbf78 r8 : 00000000
r7 : 00000009 r6 : df400000 r5 : 01c40900 r4 : 00000040
r3 : e1040000 r2 : 00000350 r1 : 00000000 r0 : 00000005
Flags: nZCv IRQs on FIQs on Mode SVC_32 Segment user
Control: 5317F Table: 86C74000 DAC: 00000015
Process sh (pid: 972, stack limit = 0xc08ca1a0)
Stack: (0xc08cbea0 to 0xc08cc000)
bea0: 0000000f 00000000 00000005 00000005 00000009 c02f2854 c08cbeec
c08cbec8
bec0: c006fea0 c0044c64 c0052c04 c71b6000 c02f2844 00000005 00000009
c02f2830
bee0: c08cbf14 c08cbef0 c0070140 c006fe48 0000000a 40018000 c6c3cb20
00000000
bf00: c6c3cb38 c6c38680 c08cbf24 c08cbf18 c00c92fc c00700c4 c08cbf54
c08cbf28
bf20: c00c95ec c00c92e0 00000000 0000000a c6c38680 40018000 c08cbf78
c00362f4
bf40: c08ca000 00900004 c08cbf74 c08cbf58 c0092ec0 c00c94ec 00000000
00000000
bf60: c6c38680 00000004 c08cbfa4 c08cbf78 c0092fb4 c0092e10 00000000
00000000
bf80: c0092444 00000000 00017a80 0000000a 4020c798 40018000 00000000
c08cbfa8
bfa0: c0035b60 c0092f7c 0000000a 4020c798 00000001 40018000 0000000a
00000000
bfc0: 0000000a 4020c798 40018000 0000000a 400178c0 00000a5c 4020c000
000bd744
bfe0: 00000000 befff724 401a5a4c 401a5a68 60000010 00000001 04000000
ffffffff
Backtrace:
[<c0044c54>] (davinci_clk_at24MHz+0x0/0x23c) from [<c006fea0>]
(enter_state+0x68/0x1cc)
r8 = C02F2854 r7 = 00000009 r6 = 00000005 r5 = 00000005
r4 = 00000000
[<c006fe38>] (enter_state+0x0/0x1cc) from [<c0070140>]
(state_store+0x8c/0xa0)
r8 = C02F2830 r7 = 00000009 r6 = 00000005 r5 = C02F2844
r4 = C71B6000
[<c00700b4>] (state_store+0x0/0xa0) from [<c00c92fc>]
(subsys_attr_store+0x2c/0x38)
[<c00c92d0>] (subsys_attr_store+0x0/0x38) from [<c00c95ec>]
(sysfs_write_file+0x110/0x15c)
[<c00c94dc>] (sysfs_write_file+0x0/0x15c) from [<c0092ec0>]
(vfs_write+0xc0/0xf8)
[<c0092e00>] (vfs_write+0x0/0xf8) from [<c0092fb4>] (sys_write+0x48/0x74)
r7 = 00000004 r6 = C6C38680 r5 = 00000000 r4 = 00000000
[<c0092f6c>] (sys_write+0x0/0x74) from [<c0035b60>]
(ret_fast_syscall+0x0/0x2c)
r6 = 40018000 r5 = 4020C798 r4 = 0000000A
Code: e5934900 e59f61c0 e59f51c0 e3c44001 (e7845006)
MontaVista(R) Linux(R) Professional Edition 4.0.1 (0502020)
192.168.0.104 login:
I found that when I use davinci_readl() function it works fine. But when I
use davinci_writel() function to write the same read register it gives the
kernel dumt.
>>>>>>davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt & ~BIT(0));
////(Hangs at this line)
Please can anyone help?
thanks,
azam.
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