Hi All: I want to test the CCD Controller in DM6446, I just want to generate the IRQ_VDINT1 first, I have replace the vdint1_isr with a simple code: cat /proc/interrupts [email protected]:/opt# cat /proc/interrupts CPU0 0: 0 AINTC vpfe_capture 1: 0 AINTC scull_read 4: 0 AINTC dm644xh3a_aew, dm644xh3a_af
and I have check the Interrupt Enable Register 0 to ensure the VDINT1 is enable. below is my code, but after running, the interrupts in /proc/interrupts still is 0 : 1: 0 AINTC scull_read I think may be the init CCD code missing some important reg, Could you help me ? Thanks. ********************************************************* ccdc_reset() ; ccdc_disable_vport(); /* Disable latching function registers on VSYNC */ regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG); /* Configure the vertical sync polarity(SYN_MODE.VDPOL) */ syn_mode = ( 0 & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT; //0:Positive /* Configure the horizontal sync polarity (SYN_MODE.HDPOL) */ syn_mode |= (0 & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT; //0:Positive /* Configure frame id polarity (SYN_MODE.FLDPOL) */ syn_mode |= (0 & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT;//0:Positive /* Configure frame format(progressive or interlace) SYN_MODE.FLDMODE*/ syn_mode |= (0 & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT; //0:progressiv /* Configure the data size(SYNMODE.DATSIZ) */ syn_mode |= (6 & CCDC_DATA_SZ_MASK) << CCDC_DATA_SZ_SHIFT; //6:10 bits /* Configure pixel format (Input mode) SYNMODE.INPMOD*/ syn_mode |= (0 & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT; //0:CCD raw data /* Configure VP2SDR bit of syn_mode = 0 */ syn_mode &= CCDC_VP2SDR_DISABLE; /* Enable write enable bit */ syn_mode |= CCDC_WEN_ENABLE; //enable CCD raw data is written to SDRAM /* Disable output to resizer */ syn_mode &= CCDC_SDR2RSZ_DISABLE; /* enable internal timing generator */ //If VD/HD are defined as output, activates internal timing generator. //If VD/HD are defined as inputs, activates internal timing generator to synchronize with VD/HD. syn_mode |= CCDC_VDHDEN_ENABLE; regw((94 << CCDC_HORZ_INFO_SPH_SHIFT) | 752, HORZ_INFO); regw((0 << CCDC_VERT_START_SLV0_SHIFT) | 0, VERT_START); regw(480, VERT_LINES); /* configure VDINT0 and VDINT1 */ /* VDINT1 will be at half of image height */ regw((0 << CCDC_VDINT_VDINT0_SHIFT) |(240 & CCDC_VDINT_VDINT1_MASK), VDINT); /* Initially disable FPC:Fault Pixel Correction */ regw(CCDC_FPC_DISABLE, FPC); /* Configure the color pattern according to mt9t001 sensor */ regw(CCDC_COLPTN_VAL, COLPTN); /* Set value for SDOFST */ regw(PROGRESSIVE_NO_IMAGE_INVERT, SDOFST); regw(syn_mode, SYN_MODE); /* enable CCDC */ ccdc_enable(1);
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