Sergei Shtylyov <[email protected]> writes: > Add support for Texas Instuments Communication Port Programming Interface 4.1 > (CPPI 4.1) used on OMAP-L1x/DA8xx. > > At this moment, only the DMA controller and queue manager are supported. > Support for the buffer manager is lacking but this chip doesn't have it > anyway. > > Signed-off-by: Sergei Shtylyov <[email protected]>
Looks mostly OK, some minor nits below. [...] > Index: linux-davinci/arch/arm/mach-davinci/cppi41.c > =================================================================== > --- /dev/null > +++ linux-davinci/arch/arm/mach-davinci/cppi41.c > @@ -0,0 +1,797 @@ > +/* > + * CPPI 4.1 support > + * > + * Copyright (C) 2008-2009 MontaVista Software, Inc. <[email protected]> > + * > + * Based on the PAL CPPI 4.1 implementation > + * Copyright (C) 1998-2006 Texas Instruments Incorporated > + * > + * This file contains the main implementation for CPPI 4.1 common > peripherals, > + * including the DMA Controllers and the Queue Managers. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + */ > + > +#include <linux/io.h> > +#include <linux/init.h> > +#include <linux/module.h> > +#include <linux/dma-mapping.h> > + > +#include <mach/cppi41.h> > + > +#undef CPPI41_DEBUG > + > +#ifdef CPPI41_DEBUG > +#define DBG(format, args...) printk(format, ##args) > +#else > +#define DBG(format, args...) > +#endif Please drop custom debug macros in favor of dev_debug() (or pr_debug() in this case.) [...] > +/* > + * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel > + */ > +void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj, > + struct cppi41_rx_ch_cfg *cfg) > +{ > + void __iomem *base = rx_ch_obj->base_addr; > + u32 val = __raw_readl(rx_ch_obj->base_addr); > + > + val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) & > + DMA_CH_RX_SOP_OFFSET_MASK) | > + ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) & > + DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) | > + ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) & > + DMA_CH_RX_ERROR_HANDLING_MASK) | > + ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) & > + DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) | > + ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) & > + DMA_CH_RX_DEFAULT_RQ_QNUM_MASK); > + > + rx_ch_obj->global_cfg = val; > + __raw_writel(val, base); > + DBG("Rx channel global configuration @ %p, value written: %x, " > + "value read: %x\n", base, val, __raw_readl(base)); > + > + base -= DMA_CH_RX_GLOBAL_CFG_REG(0); > + > + /* > + * Set up the packet configuration register > + * based on the descriptor type... > + */ > + switch (cfg->default_desc_type) { > + case DMA_CH_RX_DEFAULT_DESC_EMBED: > + val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr << > + DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) & > + DMA_CH_RX_EMBED_FDQ_QMGR_MASK) | > + ((cfg->cfg.embed_pkt.fd_queue.q_num << > + DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) & > + DMA_CH_RX_EMBED_FDQ_QNUM_MASK) | > + ((cfg->cfg.embed_pkt.num_buf_slot << > + DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) & > + DMA_CH_RX_EMBED_NUM_SLOT_MASK) | > + ((cfg->cfg.embed_pkt.sop_slot_num << > + DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) & > + DMA_CH_RX_EMBED_SOP_SLOT_MASK); > + > + __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0)); > + DBG("Rx channel embedded packet configuration B @ %p, " > + "value written: %x\n", > + base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val); > + > + val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool << > + DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) & > + DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr << > + DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) & > + DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool << > + DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) & > + DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr << > + DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) & > + DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool << > + DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) & > + DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr << > + DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) & > + DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool << > + DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) & > + DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) | > + ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr << > + DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) & > + DMA_CH_RX_EMBED_FBP_BMGR_MASK(3)); An inline function to generate these masks/values might make this and the others more readable, but your call. > + __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0)); > + DBG("Rx channel embedded packet configuration A @ %p, " > + "value written: %x\n", > + base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val); > + break; > + case DMA_CH_RX_DEFAULT_DESC_HOST: > + val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num << > + DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) & > + DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) | > + ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr << > + DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) & > + DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) | > + ((cfg->cfg.host_pkt.fdb_queue[1].q_num << > + DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) & > + DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) | > + ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr << > + DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) & > + DMA_CH_RX_HOST_FDQ_QMGR_MASK(1)); > + > + __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0)); > + DBG("Rx channel host packet configuration A @ %p, " > + "value written: %x\n", > + base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val); > + > + val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num << > + DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) & > + DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) | > + ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr << > + DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) & > + DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) | > + ((cfg->cfg.host_pkt.fdb_queue[3].q_num << > + DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) & > + DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) | > + ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr << > + DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) & > + DMA_CH_RX_HOST_FDQ_QMGR_MASK(3)); > + > + __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0)); > + DBG("Rx channel host packet configuration B @ %p, " > + "value written: %x\n", > + base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val); > + break; > + case DMA_CH_RX_DEFAULT_DESC_MONO: > + val = ((cfg->cfg.mono_pkt.fd_queue.q_num << > + DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) & > + DMA_CH_RX_MONO_FDQ_QNUM_MASK) | > + ((cfg->cfg.mono_pkt.fd_queue.q_mgr << > + DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) & > + DMA_CH_RX_MONO_FDQ_QMGR_MASK) | > + ((cfg->cfg.mono_pkt.sop_offset << > + DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) & > + DMA_CH_RX_MONO_SOP_OFFSET_MASK); > + > + __raw_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0)); > + DBG("Rx channel monolithic packet configuration @ %p, " > + "value written: %x\n", > + base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val); > + break; > + } > +} > +EXPORT_SYMBOL(cppi41_rx_ch_configure); Kevin _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
