Hemant Pedanekar <[email protected]> writes:
> Note that configuration option CONFIG_DAVINCI_RESET_CLOCKS should _not_ be
> selected if kernel is being built for DM646x PCI target. Slecting this option
> will disable the PCI PSC during kernel boot, thus preventing any access to PCI
> backend configuration (e.g., if PCI window needs to be changed). This problem
> is
> not applicable when kernel is loaded on Dm646x PCI host since the host setup
> code would call clk_enable explicitly.
>
> Signed-off-by: Hemant Pedanekar <[email protected]>
Based on the changelog doesn't really belong here. I would
recommend an additional patch to board-dm646x-evm.c which adds a
function to enable PCI target support. This function would be
documented with the above changelog and simply do a clk_get/clk_enable
on the PCI clock.
We could maybe use or extend the pci= kernel command line argument to
trigger this function.
The rest of the patch looks mostly ok...
> ---
> arch/arm/mach-davinci/dm646x.c | 11 +++++++++++
> arch/arm/mach-davinci/include/mach/mux.h | 6 ++++++
> 2 files changed, 17 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
> index 8fa2803..99f4d33 100644
> --- a/arch/arm/mach-davinci/dm646x.c
> +++ b/arch/arm/mach-davinci/dm646x.c
> @@ -306,6 +306,12 @@ static struct clk vpif1_clk = {
> .flags = ALWAYS_ENABLED,
> };
>
> +static struct clk pci_clk = {
> + .name = "pci",
> + .parent = &pll1_sysclk2,
> + .lpsc = DM646X_LPSC_PCI,
> +};
> +
Can you please group this with the other PLL1 SYSCLK2 clocks please.
Like right after edma_tc3_clk.
> struct davinci_clk dm646x_clks[] = {
> CLK(NULL, "ref", &ref_clk),
> CLK(NULL, "aux", &aux_clkin),
> @@ -342,6 +348,7 @@ struct davinci_clk dm646x_clks[] = {
> CLK(NULL, "pwm1", &pwm1_clk),
> CLK(NULL, "timer0", &timer0_clk),
> CLK(NULL, "timer1", &timer1_clk),
> + CLK(NULL, "pci", &pci_clk),
> CLK("watchdog", NULL, &timer2_clk),
> CLK("palm_bk3710", NULL, &ide_clk),
> CLK(NULL, "vpif0", &vpif0_clk),
> @@ -409,6 +416,10 @@ static const struct mux_config dm646x_pins[] = {
> #ifdef CONFIG_DAVINCI_MUX
> MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
>
> +MUX_CFG(DM646X, PCIEN, 0, 0, 7, 4, true)
> +
> +MUX_CFG(DM646X, HPI32EN, 0, 0, 7, 2, true)
> +
> MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
>
> MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
> diff --git a/arch/arm/mach-davinci/include/mach/mux.h
> b/arch/arm/mach-davinci/include/mach/mux.h
> index 368fca6..7ea97cf 100644
> --- a/arch/arm/mach-davinci/include/mach/mux.h
> +++ b/arch/arm/mach-davinci/include/mach/mux.h
> @@ -94,6 +94,12 @@ enum davinci_dm646x_index {
> /* ATA function */
> DM646X_ATAEN,
>
> + /* PCI function */
> + DM646X_PCIEN,
> +
> + /* HPI 32-bit */
> + DM646X_HPI32EN,
> +
> /* AUDIO Clock */
> DM646X_AUDCK1,
> DM646X_AUDCK0,
Kevin
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