On Thu, 2010-01-07 at 16:18 +0100, Raúl Sánchez Siles wrote: > Hello All: > > Reviewing DM355 documentation I think I've comem across a discrepancy with > respect to the VPSS Clock Mux Control Register. This register is defined in 2 > different documents. > > · SPRUFB3 (Sept 2007) ARM Subsystem Reference, section: 9.10.19 > VPSS_CLK_CTRL - VPSS Clock Mux Control. Located at system control module with > address 0x01C40000+0x44 > > · SPRUF72C (Oct2008) Video Processing Backend, section 3.1.1.4 > VPSS Clock Mux Control Register (VPSS_CLK_CTRL). Located at VPSS Subsystem > with address 0x01C70004 > > The point is that I'm not sure which one is the right address and register, > since I'm getting confusing and contradicting behaviours changing their > fields. Moreover the default values I get on each of them when system is > booted are different and correspond to and invalid/reserved combination of > settings. > > Any indication and comments are appreciated. > > Thanks and regards, > > Note: Please CC, since I'm not subscribed to the list. >
These two documents describes different areas of the hardware. Unfortunately, the same name is used for both. A way to look at it is that one is use for clock control outside of video processing block, and the other is inside of video processing block. Regards, Steve _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
