Gaer, A. wrote:
> Hi!
>
> It seems like the layout of OOB/4-Bit-ECC data in NAND flash differs
> from RBL/UBL to u-boot/linux (at least on a DM365 device). Is there
> any good reason for this?

Hi, just to say I am working in similar areas (trying to understand what the 
hell TI are doing with their NAND ECC layouts), on DM355 so far but may start 
looking at DM365 before long. So I am interested in whatever progress you make.

The DM355 silicon errata admits that the DM355 RBL doesn't actually check 4-bit 
ECC at all. But the layout used by UBL, u-boot and linux is all messed up.
There is some stuff about DM365 RBL ECC handling in the DM365 silicon errata 
too, not the same thing, but maybe of interest.

> As far as I understand, the RBL/UBL uses this layout (2048 byte
> pages):

What is your understanding based on? What wrote that format? Are you reading 
that from flash or working it out by inspecting code?

> The different layout means that it is impossible to update UBL/u-boot
> from u-boot or linux.

Have you tried? On DM355 at least, it seems this would actually work.

> Another question: 512 byte pages in linux seem to have a really funny
> oob layout
>
> EEEEEXEE
> XXXXXEEE
>
> Does anybody know the reason for that? (I know the 6th byte is the
> manufacturer bad-block marker. But why not just put the ECC data into
> the last 10 byte of oob like RBL/UBL do it?)

Good luck getting good answers to these questions.

This might be worth some wiki documenting when it becomes clearer.

--
Jon Povey
[email protected]

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