David Brownell wrote:
>> Because there isn't an actual IRQ for each pin,
>> they need to be virtual.
>
> Actually, some of them could be "real" IRQs
> instead of being dispatched through the GPIO
> bank IRQ (which is a "real" IRQ, of course).
>
> But that gets messy.  At one point it didn't
> work at all in Linux.  It should work now, but as
> a rule you should expect IRQs associated with
> DaVinci GPIOs to be dispatched through some
> top-level bank IRQ ... most Linux platforms do
> the same thing (so doing anything else is what
> should be a surprise).

I suppose that's just my inexperience showing, then.

It does seem confusing that there are two sets of values called "irq" used in 
the kernel code, one agreeing with the datasheet and one made-up token. I'm 
sure it's all straightforward when you're used to it, and really who is to say 
what's a "real" IRQ anyway, as the AINTC is a Davinci-specific thing as much as 
banked GPIO interrupts, the ARM only having two really hard interrupts.

It made more sense as the dust settled. A shame it violates the principle of 
least surprise (to my eyes) but I see why and can't think of a good clean fix 
without another layer of abstraction.

Shutting up.

--
Jon Povey
[email protected]

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