Hi, On Tue, Jun 22, 2010 at 13:01:03, Jon Povey wrote: > Move the interrupt enable after the first byte load for TX, as it > was racing with the interrupt handler and corrupting dev->buf_len > for messages > 1 byte. > > Tested on DM355. > > Signed-off-by: Jon Povey <[email protected]> > --- > The race seems to have been introduced by > 869e6692d527983958216f13c3c8e095791909df > > This fixes the problem for me, but someone from TI might want to comment > on the validity of starting the transfer before enabling the RDY interrupts. > Any possibility of losing interrupts? >
This fix can cause interrupts to be missed as there will be a race between writing to DXR and setting of interrupts. I think you can decrement dev->buf_len before writing to DXR register. This should resolve the original race condition which you had encountered. Regards, Sudhakar _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
