Sudhakar Rajashekhara wrote:
> On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the
> 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and
> before waiting for the NAND Flash status register to be equal to 1, 2
> or 3, we have to wait till the ECC HW goes to correction state.
> Without this wait, ECC correction calculations will not be proper.
>
> This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and
> DM365 EVMs.
>
> Signed-off-by: Sudhakar Rajashekhara <[email protected]>
> Acked-by: Sneha Narnakaje <[email protected]>
> Cc: David Woodhouse <[email protected]>
> Signed-off-by: Andrew Morton <[email protected]>
Have these people acked and signed off this new version of the patch?
> Since v1:
> a. Timeout has been changed from 100 msec to 100 usec.
> b. Comment above the do, while loop was not matching the code.
> This has been corrected.
> c. Initialization of 'timeo' variable has been moved down.
> d. It was observed that, while calculating the time in the loop,
> if there is a context switch between setting the
> 4BITECC_ADD_CALC_START bit and reading of ECC_STATE field, then
> the loop will not come out until the timeout happens. To prevent
> the context switch, spin_lock_irqsave and spin_unlock_irqrestore
> are used.
d. means interrupts are disabled for up to 100us while waiting for ECC.
Doesn't sound good if it can be avoided.
How about instead of spinlock, set timeo first time inside the loop?
>From this:
+ timeo = jiffies + usecs_to_jiffies(100);
+ do {
+ ecc_state = (davinci_nand_readl(info,
+ NANDFSR_OFFSET) >> 8) & 0x0f;
+ cpu_relax();
+ } while ((ecc_state < 4) && time_before(jiffies, timeo));
+ spin_unlock_irqrestore(&ecc_spin_lock, flags);
To something like:
+ timeo = 0;
+ do {
+ ecc_state = (davinci_nand_readl(info,
+ NANDFSR_OFFSET) >> 8) & 0x0f;
+ if (!timeo)
+ timeo = jiffies + usecs_to_jiffies(100);
+ cpu_relax();
+ } while ((ecc_state < 4) && time_before(jiffies, timeo));
Sorry if my mailer has messed up the formatting. Hopefuly readable.
--
Jon Povey
[email protected]
Racelogic is a limited company registered in England. Registered number 2743719
.
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks,
MK18 1TB .
The information contained in this electronic mail transmission is intended by
Racelogic Ltd for the use of the named individual or entity to which it is
directed and may contain information that is confidential or privileged. If you
have received this electronic mail transmission in error, please delete it from
your system without copying or forwarding it, and notify the sender of the
error by reply email so that the sender's address records can be corrected. The
views expressed by the sender of this communication do not necessarily
represent those of Racelogic Ltd. Please note that Racelogic reserves the right
to monitor e-mail communications passing through its network
_______________________________________________
Davinci-linux-open-source mailing list
[email protected]
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
