On Tue, Jul 27, 2010 at 6:08 AM, Jaya krishnan <[email protected]> wrote: > > Hi > We have some design issues with interfacing DM6467 McASP to a third party > DAC.(CS4353- A paasive DAC with stereo output) > We actually tried to replace AIC33 with CS4353. In the board which uses > AIC33 , McASP is receiving Serial clk and FS from AIC33. > But in our board, we can't provide Serial clk and FS from DAC and hence > McASP gives FS to DAC . Serial clock is provided by > a CDCE949 clk synthesizer. (I have attached the connection diagram). > The problem is , the FS generated by McASP is governed by the follwoing > relationship > FS= Serial clk/(slot size * No of Slots) > I have given serial clk=256KHz, slot size=32, I2S and FS=4KHz. And I get > the output quite normally. > I am confused in this. > 1) How can a data (speech )sampled at 8KHz, 16 bit sample width plays > normally at FS= 4KHz?
As you point out, at FS=4kHz, serial clock is 256KHz which provide enough cycles to shift out 8Kb/s of data. > If I change the slot size to 16 bit , FS becomes 8 KHz, and the audio > plays at double speed. > 2) Why is it like that? May want to check out the DMA settings. I suspect DMA engine is still grabbing 32 bits at a time but at double speed. Regards, Steve _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
