This patch modifies the sysclk rate setting code to use the divider mask specified in pll_data. Without this, devices with different divider ranges (e.g. tnetv107x) fail.
Signed-off-by: Cyril Chemparathy <[email protected]> --- arch/arm/mach-davinci/clock.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 01ba080..e4e3af1 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) ratio--; } - if (ratio > PLLDIV_RATIO_MASK) + if (ratio > pll->div_ratio_mask) return -EINVAL; do { @@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) } while (v & PLLSTAT_GOSTAT); v = __raw_readl(pll->base + clk->div_reg); - v &= ~PLLDIV_RATIO_MASK; + v &= ~pll->div_ratio_mask; v |= ratio | PLLDIV_EN; __raw_writel(v, pll->base + clk->div_reg); -- 1.7.0.4 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
