On Fri, Dec 03, 2010 at 14:31:22, Nori, Sekhar wrote: > > PLLOUT is defined in the table as the PLL Output frequency, it's not clear > > if that's before or after the post divider (seems like before given the > > block > > diagram in Figure 6-9 and a minimum value of 300 MHz). > > Yup, PLLOUT is before the post divider. > > > > > This OPP(372) results in a PLL of 744 MHz prior to the post divider. > > > > Is this a problem? Or am I reading the spec wrong? > > Good point, I had this question too. With the current spec, it is not > possible to achieve any frequency between 300-400MHz on the ARM. However, > 375 MHz parts are available.
Okay, the OMAP-L138 datasheet shows the range as 300-600MHz and AM1808 shows the range as 400-600MHz. Most likely the AM1808 spec will be updated and 372 MHz will be achieved using: 24 (crystal) / 2 (pre-div) * 31 (pllm) / 1 (post-div). I will confirm this with h/w folks and update the code (and comments). Thanks Mike for pointing out. Best Regards, Sekhar _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
