Hello Subhasish, Here are some observations, for what they're worth... (IANAE)
On 12/31/2010 07:18 AM, Subhasish Ghosh wrote: > suart_api.c - PRU read/write/config/init/deinit API's > suart_utils.c - McASP read/write/config/init/deinit API's > ti_omapl_pru_suart.c - Linux tty serial driver > > Signed-off-by: Subhasish <[email protected]> > --- > drivers/serial/omapl_pru/Kconfig | 20 + > drivers/serial/omapl_pru/Makefile | 9 + > drivers/serial/omapl_pru/omapl_suart_board.h | 50 + > drivers/serial/omapl_pru/suart_api.c | 2758 > +++++++++++++++++++++++++ > drivers/serial/omapl_pru/suart_api.h | 325 +++ > drivers/serial/omapl_pru/suart_err.h | 48 + > drivers/serial/omapl_pru/suart_pru_regs.h | 152 ++ > drivers/serial/omapl_pru/suart_utils.c | 363 ++++ > drivers/serial/omapl_pru/suart_utils.h | 62 + > drivers/serial/omapl_pru/ti_omapl_pru_suart.c | 1026 +++++++++ > 10 files changed, 4813 insertions(+), 0 deletions(-) > create mode 100644 drivers/serial/omapl_pru/Kconfig > create mode 100644 drivers/serial/omapl_pru/Makefile > create mode 100644 drivers/serial/omapl_pru/omapl_suart_board.h > create mode 100644 drivers/serial/omapl_pru/suart_api.c > create mode 100644 drivers/serial/omapl_pru/suart_api.h > create mode 100644 drivers/serial/omapl_pru/suart_err.h > create mode 100644 drivers/serial/omapl_pru/suart_pru_regs.h > create mode 100644 drivers/serial/omapl_pru/suart_utils.c > create mode 100644 drivers/serial/omapl_pru/suart_utils.h > create mode 100644 drivers/serial/omapl_pru/ti_omapl_pru_suart.c > > diff --git a/drivers/serial/omapl_pru/Kconfig > b/drivers/serial/omapl_pru/Kconfig > new file mode 100644 > index 0000000..f984bc5 > --- /dev/null > +++ b/drivers/serial/omapl_pru/Kconfig > @@ -0,0 +1,20 @@ > +# > +# SUART Kernel Configuration > +# > + > +config SERIAL_SUART_OMAPL_PRU > + depends on ARCH_DAVINCI && ARCH_DAVINCI_DA850 > + select SERIAL_CORE > + tristate "PRU based SoftUART emulation for OMAPL" > + ---help--- > + Enable this to emulate a UART controller on the PRU of OMAPL. > + Enable this to emulate a UART controller on the PRU of OMAPL. > + If not sure, mark N > + > +config OMAPL_SUART_MCASP > + int "McASP number" > + depends on ARCH_DAVINCI && ARCH_DAVINCI_DA830 && SERIAL_SUART_OMAPL_PRU > + default "0" > + ---help--- > + Enter the McASP number to use with SUART (0, 1 or 2). > + You will need to recompile the kernel if this is changed. > diff --git a/drivers/serial/omapl_pru/Makefile > b/drivers/serial/omapl_pru/Makefile > new file mode 100644 > index 0000000..3378e0f > --- /dev/null > +++ b/drivers/serial/omapl_pru/Makefile > @@ -0,0 +1,9 @@ > +# > +# Makefile for SoftUART emulation > +# > + > +suart_emu-objs := ti_omapl_pru_suart.o \ > + suart_api.o \ > + suart_utils.o > + > +obj-$(CONFIG_SERIAL_SUART_OMAPL_PRU) += suart_emu.o > diff --git a/drivers/serial/omapl_pru/omapl_suart_board.h > b/drivers/serial/omapl_pru/omapl_suart_board.h > new file mode 100644 > index 0000000..0d29623 > --- /dev/null > +++ b/drivers/serial/omapl_pru/omapl_suart_board.h > @@ -0,0 +1,50 @@ > +/* > + * Copyright (C) 2010 Texas Instruments Incorporated > + * Author: [email protected] > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation version 2. > + * > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, > + * whether express or implied; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * General Public License for more details. > + */ > + > +#ifndef _OMAPL_SUART_BOARD_H_ > +#define _OMAPL_SUART_BOARD_H_ > + > +#define PRU_SUART1_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART1_CONFIG_RX_SER (PRU_SUART_SERIALIZER_NONE) > +#define PRU_SUART1_CONFIG_TX_SER (PRU_SUART_SERIALIZER_NONE) > + > +#define PRU_SUART2_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART2_CONFIG_RX_SER (PRU_SUART_SERIALIZER_7) > +#define PRU_SUART2_CONFIG_TX_SER (PRU_SUART_SERIALIZER_8) > + > +#define PRU_SUART3_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART3_CONFIG_RX_SER (PRU_SUART_SERIALIZER_9) > +#define PRU_SUART3_CONFIG_TX_SER (PRU_SUART_SERIALIZER_10) > + > +#define PRU_SUART4_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART4_CONFIG_RX_SER (PRU_SUART_SERIALIZER_NONE) > +#define PRU_SUART4_CONFIG_TX_SER (PRU_SUART_SERIALIZER_NONE) > + > +#define PRU_SUART5_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART5_CONFIG_RX_SER (PRU_SUART_SERIALIZER_NONE) > +#define PRU_SUART5_CONFIG_TX_SER (PRU_SUART_SERIALIZER_NONE) > + > +#define PRU_SUART6_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART6_CONFIG_RX_SER (PRU_SUART_SERIALIZER_NONE) > +#define PRU_SUART6_CONFIG_TX_SER (PRU_SUART_SERIALIZER_NONE) > + > +#define PRU_SUART7_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART7_CONFIG_RX_SER (PRU_SUART_SERIALIZER_NONE) > +#define PRU_SUART7_CONFIG_TX_SER (PRU_SUART_SERIALIZER_NONE) > + > +#define PRU_SUART8_CONFIG_DUPLEX (ePRU_SUART_HALF_TX | > ePRU_SUART_HALF_RX) > +#define PRU_SUART8_CONFIG_RX_SER (PRU_SUART_SERIALIZER_NONE) > +#define PRU_SUART8_CONFIG_TX_SER (PRU_SUART_SERIALIZER_NONE) > + > +#endif /* End of _OMAPL_SUART_BOARD_H_ */ > diff --git a/drivers/serial/omapl_pru/suart_api.c > b/drivers/serial/omapl_pru/suart_api.c > new file mode 100644 > index 0000000..c46d6b4 > --- /dev/null > +++ b/drivers/serial/omapl_pru/suart_api.c > @@ -0,0 +1,2758 @@ > +/* > + * Copyright (C) 2010 Texas Instruments Incorporated > + * Author: Jitendra Kumar <[email protected]> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation version 2. > + * > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, > + * whether express or implied; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * General Public License for more details. > + */ > + > +#include <linux/types.h> > +#include <mach/pru/pru.h> > +#include "suart_api.h" > +#include "suart_pru_regs.h" > +#include "omapl_suart_board.h" > +#include "suart_utils.h" > +#include "suart_err.h" > + > +static u8 gUartStatuTable[8]; > +static arm_pru_iomap pru_arm_iomap; > + > +#if (PRU_ACTIVE == BOTH_PRU) > +void pru_set_ram_data(arm_pru_iomap *arm_iomap_pru) > +{ > + PRU_SUART_RegsOvly pru_suart_regs = > + (PRU_SUART_RegsOvly) arm_iomap_pru->pru_io_addr; > + u32 *pu32SrCtlAddr = (u32 *)(arm_iomap_pru->mcasp_io_addr + 0x180); > + pru_suart_tx_cntx_priv *pru_suart_tx_priv = NULL; > + pru_suart_rx_cntx_priv *pru_suart_rx_priv = NULL; > + u8 *pu32_pru_ram_base = (u8 *)arm_iomap_pru->pru_io_addr; > + /* RX PRU - 0 Chanel 0 context information */ > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART1_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART1_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART1_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* > + * RX is active by default, write the dummy received data at > + * PRU RAM addr 0x1FC to avoid memory corruption. > + */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART1 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x090); > + pru_suart_rx_priv->asp_rbuf_base = > + (u32)(MCASP_RBUF_BASE_ADDR + (PRU_SUART1_CONFIG_RX_SER > << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART1_CONFIG_RX_SER << 2)); > + > + /* Chanel 1 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART2_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART2_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART2_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART2 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x0B0); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + > (PRU_SUART2_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART2_CONFIG_RX_SER << 2)); > + It seems like all (or at least a fair amount of) initialization of the contexts for all channels could be accomplished in a loop instead of replicating the code. Perhaps a static lookup table(s) could be used for initialization of port specific parameters? It would seem like there might be an opportunity to reduce the code footprint a bit. > + /* Chanel 2 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART3_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART3_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART3_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy > + * received data at PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x0D0); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART3_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART3_CONFIG_RX_SER << 2)); > + > + /* Chanel 3 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART4_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART4_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART4_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART4 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x0F0); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART4_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART4_CONFIG_RX_SER << 2)); > + > + /* Chanel 4 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART5_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART5_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART5_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART5 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x110); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART5_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART5_CONFIG_RX_SER << 2)); > + > + /* Chanel 5 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART6_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART6_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART6_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x130); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART6_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = > + (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART6_CONFIG_RX_SER << 2)); > + > + /* Chanel 6 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART7_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART7_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART7_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART7 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x150); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART7_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART7_CONFIG_RX_SER << 2)); > + > + /* Chanel 7 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART8_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = > + SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART8_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART8_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data at > + * PRU RAM addr 0x1FC to avoid memory corruption */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART8 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x170); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART8_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART8_CONFIG_RX_SER << 2)); > + > + /* ****************** PRU1 RAM BASE ADDR ************************ */ > + pru_suart_regs = (PRU_SUART_RegsOvly) > + (arm_iomap_pru->pru_io_addr + 0x2000); > + pu32_pru_ram_base = (u8 *)(arm_iomap_pru->pru_io_addr + 0x2000); > + > + /* ******************* TX PRU - 1 *********************** */ > + /* Channel 0 context information */ > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART1_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART1_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART1_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART1 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x0B0); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART1_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART1_CONFIG_TX_SER << 2)); > + /* SUART1 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x0090; Same comment here... > + > + /* Channel 1 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART2_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART2_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART2_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART2 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x0DC); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART2_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART2_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->buff_addr = 0x00BC; > + > + /* Channel 2 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART3_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART3_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART3_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART3 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x108); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART3_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART3_CONFIG_TX_SER << 2)); > + /* SUART3 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x00E8; > + > + /* Channel 3 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART4_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART4_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART4_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART4 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x134); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART4_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART4_CONFIG_TX_SER << 2)); > + /* SUART4 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x0114; > + > + /* Channel 4 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART5_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART5_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART5_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART5 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x160); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART5_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART5_CONFIG_TX_SER << 2)); > + /* SUART5 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x0140; > + > + /* Channel 5 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART6_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART6_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART6_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART6 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x18C); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART6_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART6_CONFIG_TX_SER << 2)); > + /* SUART6 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x016C; > + > + /* Channel 6 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART7_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART7_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART7_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART7 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x1B8); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART7_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART7_CONFIG_TX_SER << 2)); > + /* SUART7 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x0198; > + > + /* Channel 7 context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART8_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART8_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART8_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART8 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x1E4); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART8_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART8_CONFIG_TX_SER << 2)); > + /* SUART8 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x01C4; > +} > +#else > +void pru_set_ram_data(arm_pru_iomap *arm_iomap_pru) > +{ > + > + PRU_SUART_RegsOvly pru_suart_regs = (PRU_SUART_RegsOvly) > + arm_iomap_pru->pru_io_addr; > + u32 *pu32SrCtlAddr = (u32 *)(arm_iomap_pru->mcasp_io_addr + 0x180); > + pru_suart_tx_cntx_priv *pru_suart_tx_priv = NULL; > + pru_suart_rx_cntx_priv *pru_suart_rx_priv = NULL; > + u8 *pu32_pru_ram_base = (u8 *)arm_iomap_pru->pru_io_addr; > + > + /* ***************** UART 0 ************************ */ > + /* Channel 0 context information is Tx */ > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART1_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART1_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART1_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART1 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x0B0); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART1_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART1_CONFIG_TX_SER << 2)); > + /* SUART1 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x0090; > + > + /* Channel 1 is Rx context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART1_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART1_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART1_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + *at PRU RAM addr 0x1FC to avoid memory corruption > + */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART1 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x0C0); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART1_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART1_CONFIG_RX_SER << 2)); > + Same comment here... maybe an even/odd set of loops to deal with Tx/Rx? Or loop on UART setting tx and rx parameters per UART? > + /* ************** UART 1 ************************ */ > + /* Channel 2 context information is Tx */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART2_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART2_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART2_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART2 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x100); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART2_CONFIG_TX_SER << 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART2_CONFIG_TX_SER << 2)); > + /* SUART2 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x00E0; > + > + /* Channel 3 is Rx context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & PRU_SUART2_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = > + SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART2_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART2_CONFIG_RX_SER)) = > + > MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption > + */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART2 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x110); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART2_CONFIG_RX_SER << > 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART2_CONFIG_RX_SER << > 2)); > + > + /* **************** UART 2 ********************* */ > + /* Channel 4 context information is Tx */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & > PRU_SUART3_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART3_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART3_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART3 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x150); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART3_CONFIG_TX_SER << > 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART3_CONFIG_TX_SER << > 2)); > + pru_suart_tx_priv->buff_addr = 0x0130; > + > + /* Channel 5 is Rx context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & > PRU_SUART3_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART3_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART3_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption > + */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART3 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x160); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART3_CONFIG_RX_SER << > 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART3_CONFIG_RX_SER << > 2)); > + > + /* *********** UART 3 *********************** */ > + /* Channel 6 context information is Tx */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_TX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & > PRU_SUART4_CONFIG_TX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART4_CONFIG_TX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART4_CONFIG_TX_SER)) = > + MCASP_SRCTL_TX_MODE; > +#endif > + pru_suart_regs->Reserved1 = 1; > + /* SUART4 TX context base addr */ > + pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) > + (pu32_pru_ram_base + 0x1A0); > + pru_suart_tx_priv->asp_xsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART4_CONFIG_TX_SER << > 2)); > + pru_suart_tx_priv->asp_xbuf_base = (u32)(MCASP_XBUF_BASE_ADDR + > + (PRU_SUART4_CONFIG_TX_SER << > 2)); > + /* SUART4 TX formatted data base addr */ > + pru_suart_tx_priv->buff_addr = 0x0180; > + > + /* Channel 7 is Rx context information */ > + pru_suart_regs++; > + pru_suart_regs->CH_Ctrl.mode = SUART_CHN_RX; > + pru_suart_regs->CH_Ctrl.serializer_num = > + (0xF & > PRU_SUART4_CONFIG_RX_SER); > + pru_suart_regs->CH_Config1.over_sampling = SUART_DEFAULT_OVRSMPL; > + pru_suart_regs->CH_Config2.bits_per_char = 8; > +#if (PRU_SUART4_CONFIG_RX_SER == PRU_SUART_SERIALIZER_NONE) > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_DISABLED; > +#else > + pru_suart_regs->CH_TXRXStatus.chn_state = SUART_CHN_ENABLED; > + *((u32 *)(pu32SrCtlAddr + PRU_SUART4_CONFIG_RX_SER)) = > + MCASP_SRCTL_RX_MODE; > +#endif > + /* RX is active by default, write the dummy received data > + * at PRU RAM addr 0x1FC to avoid memory corruption > + */ > + pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR; > + pru_suart_regs->Reserved1 = 0; > + /* SUART4 RX context base addr */ > + pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) > + (pu32_pru_ram_base + 0x1B0); > + pru_suart_rx_priv->asp_rbuf_base = (u32)(MCASP_RBUF_BASE_ADDR + > + (PRU_SUART4_CONFIG_RX_SER << 2)); > + pru_suart_rx_priv->asp_rsrctl_base = (u32)(MCASP_SRCTL_BASE_ADDR + > + (PRU_SUART4_CONFIG_RX_SER << 2)); > +} > + > +#endif > + > +static void pru_set_rx_tx_mode(u32 pru_mode, u32 pruNum) > +{ > + > + u32 pruOffset; > + > + if (pruNum == PRU_NUM0) { > + pruOffset = PRU_SUART_PRU0_RX_TX_MODE; > + } else if (pruNum == PRU_NUM1) { > + pruOffset = PRU_SUART_PRU1_RX_TX_MODE; > + } else { > + return; > + } > + pru_ram_write_data(pruOffset, (u8 *) &pru_mode, 1, &pru_arm_iomap); > +} > + > +static void pru_set_delay_count(u32 pru_freq) > +{ > + u32 u32delay_cnt; > + > + if (pru_freq == 228) > + u32delay_cnt = 5; > + else if (pru_freq == 186) > + u32delay_cnt = 5; > + else > + u32delay_cnt = 3; > + > + /* PRU 0 */ > + pru_ram_write_data(PRU_SUART_PRU0_DELAY_OFFSET, > + (u8 *) &u32delay_cnt, 1, &pru_arm_iomap); > + > + /* PRU 1 */ > + pru_ram_write_data(PRU_SUART_PRU1_DELAY_OFFSET, > + (u8 *) &u32delay_cnt, 1, &pru_arm_iomap); > +} > + > +static s32 suart_set_pru_id(u32 pru_no) > +{ > + u32 offset; > + u16 reg_val = 0; > + > + if (0 == pru_no) > + offset = PRU_SUART_PRU0_ID_ADDR; > + else if (1 == pru_no) > + offset = PRU_SUART_PRU1_ID_ADDR; > + else > + return PRU_SUART_FAILURE; > + > + pru_ram_read_data(offset, (u8 *) ®_val, 1, &pru_arm_iomap); > + reg_val &= ~SUART_PRU_ID_MASK; > + reg_val = pru_no; > + pru_ram_write_data(offset, (u8 *) ®_val, 1, &pru_arm_iomap); > + > + return PRU_SUART_SUCCESS; > +} > + > +/* > + * suart Initialization routine > + */ > +s16 pru_softuart_init(u32 txBaudValue, > + u32 rxBaudValue, > + u32 oversampling, > + u8 *pru_suart_emu_code, > + u32 fw_size, arm_pru_iomap *arm_iomap_pru) > +{ > + u32 omapl_addr; > + u32 u32loop; > + s16 status = PRU_SUART_SUCCESS; > + s16 idx; > + s16 retval; > + > + if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) && > + (PRU1_MODE == PRU_MODE_RX_TX_BOTH)) { > + return PRU_SUART_FAILURE; > + } > + > + pru_arm_iomap.pru_io_addr = arm_iomap_pru->pru_io_addr; > + pru_arm_iomap.mcasp_io_addr = arm_iomap_pru->mcasp_io_addr; > + pru_arm_iomap.pFifoBufferPhysBase = arm_iomap_pru->pFifoBufferPhysBase; > + pru_arm_iomap.pFifoBufferVirtBase = arm_iomap_pru->pFifoBufferVirtBase; > + pru_arm_iomap.pru_clk_freq = arm_iomap_pru->pru_clk_freq; > + omapl_addr = (u32)arm_iomap_pru->mcasp_io_addr; > + /* Configure McASP0 */ > + suart_mcasp_config(omapl_addr, txBaudValue, rxBaudValue, oversampling, > + arm_iomap_pru); > + pru_enable(0, arm_iomap_pru); > + pru_enable(1, arm_iomap_pru); > + omapl_addr = (u32)arm_iomap_pru->pru_io_addr; > + for (u32loop = 0; u32loop < 512; u32loop++) { > + *(u32 *)(omapl_addr | u32loop) = 0x0; > + *(u32 *)(omapl_addr | u32loop | 0x2000) = 0x0; > + } > + pru_load(PRU_NUM0, (u32 *)pru_suart_emu_code, (fw_size / sizeof(u32)), > + arm_iomap_pru); > + pru_load(PRU_NUM1, (u32 *)pru_suart_emu_code, (fw_size / sizeof(u32)), > + arm_iomap_pru); > + retval = arm_to_pru_intr_init(); > + if (-1 == retval) > + return status; > + pru_set_delay_count(pru_arm_iomap.pru_clk_freq); > + suart_set_pru_id(PRU_NUM0); > + suart_set_pru_id(PRU_NUM1); > + pru_set_rx_tx_mode(PRU0_MODE, PRU_NUM0); > + pru_set_rx_tx_mode(PRU1_MODE, PRU_NUM1); > + pru_set_ram_data(arm_iomap_pru); > + pru_run(PRU_NUM0, arm_iomap_pru); > + pru_run(PRU_NUM1, arm_iomap_pru); > + > + /* Initialize gUartStatuTable */ > + for (idx = 0; idx < 8; idx++) { > + gUartStatuTable[idx] = ePRU_SUART_UART_FREE; > + } > + > + return status; > +} > + > +void pru_set_fifo_timeout(u32 timeout) > +{ > + pru_ram_write_data(PRU_SUART_PRU0_IDLE_TIMEOUT_OFFSET, (u8 *) &timeout, > + 2, > &pru_arm_iomap); > + pru_ram_write_data(PRU_SUART_PRU1_IDLE_TIMEOUT_OFFSET, (u8 *) &timeout, > + 2, > &pru_arm_iomap); > +} > + > +s16 pru_softuart_deinit(void) > +{ > + u32 offset; > + s16 s16retval = 0; > + u32 u32value = 0; > + > + offset = (u32)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT1 & > 0xFFFF); > + u32value = 0xFFFFFFFF; > + s16retval = pru_ram_write_data_4byte(offset, (u32 *)&u32value, 1); > + if (-1 == s16retval) > + return -1; > + offset = > + (u32)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT0 & > + 0xFFFF); > + u32value = 0xFFFFFFFF; > + s16retval = pru_ram_write_data_4byte(offset, (u32 *)&u32value, 1); > + if (-1 == s16retval) > + return -1; > + pru_disable(&pru_arm_iomap); > + > + return PRU_SUART_SUCCESS; > +} > + > +/* suart Instance open routine */ > +s16 pru_softuart_open(suart_handle hSuart) > +{ > + s16 status = PRU_SUART_SUCCESS; > + > + switch (hSuart->uartNum) { > + case PRU_SUART_UART1: > + if (gUartStatuTable[PRU_SUART_UART1 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART1_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART1_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART1_CONFIG_RX_SER; > + gUartStatuTable[PRU_SUART_UART1 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART2: > + if (gUartStatuTable[PRU_SUART_UART2 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART2_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART2_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART2_CONFIG_RX_SER; > + gUartStatuTable[PRU_SUART_UART2 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART3: > + if (gUartStatuTable[PRU_SUART_UART3 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART3_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART3_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART3_CONFIG_RX_SER; > + gUartStatuTable[PRU_SUART_UART3 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART4: > + if (gUartStatuTable[PRU_SUART_UART4 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART4_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART4_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART4_CONFIG_RX_SER; > + > + gUartStatuTable[PRU_SUART_UART4 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART5: > + if (gUartStatuTable[PRU_SUART_UART5 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART5_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART5_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART5_CONFIG_RX_SER; > + > + gUartStatuTable[PRU_SUART_UART5 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART6: > + if (gUartStatuTable[PRU_SUART_UART6 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART6_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART6_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART6_CONFIG_RX_SER; > + gUartStatuTable[PRU_SUART_UART6 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART7: > + if (gUartStatuTable[PRU_SUART_UART7 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART7_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART7_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART7_CONFIG_RX_SER; > + gUartStatuTable[PRU_SUART_UART7 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + case PRU_SUART_UART8: > + if (gUartStatuTable[PRU_SUART_UART8 - 1] == > + ePRU_SUART_UART_IN_USE) > { > + status = SUART_UART_IN_USE; > + return status; > + } else { > + hSuart->uartStatus = ePRU_SUART_UART_IN_USE; > + hSuart->uartType = PRU_SUART8_CONFIG_DUPLEX; > + hSuart->uartTxChannel = PRU_SUART8_CONFIG_TX_SER; > + hSuart->uartRxChannel = PRU_SUART8_CONFIG_RX_SER; > + gUartStatuTable[PRU_SUART_UART8 - 1] = > + ePRU_SUART_UART_IN_USE; > + } > + break; > + > + default: > + status = SUART_INVALID_UART_NUM; > + break; > + } Seems like you could reduce this code a bit by validating the hSuart->uartNum first and extracting the IN_USE status check out of the case statement. > + return status; > +} > + -Mike _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
