On Tue, Jan 04, 2011 at 17:35:27, S.Ghosh wrote: > > [SG] -- This is not actually ported code, but was developed for DSP and > Linux simultaneously on the same code base. > PRU API's were kept OS agnostic as there were plans to port it into > u-boot as well. > Incidently, some of the coders were having a DSP background and hence > the coding standard conflicts. > I have tried to cleanup as much as I can, but I guess these is more > cleanup required.
Yes please. Linux code should follow the guidelines documented in Documentation/CodingStyle and Documentation/SubmittingPatches under the kernel tree. > Also, I don't think this driver belongs under > arch/arm/mach-davinci. > As a new serial core, I'm guessing it belongs under > drivers/serial. > > > > [SG] -- The drivers are part of the TTY serial framework and not merged > into mach-davinci code at all. > In mach-davinci I have only added some common API's, these can be used > for both CAN & UART hence avoiding some code duplication. Recently on the linux-arm-kernel mailing list, I saw Russell discouraging implementation of IP drivers under arch/arm especially in light of the extensive IP reuse across architectures (within ARM and outside of ARM too). So, any common code will have to go under drivers/mfd or drivers/misc. In this list there was a lot of discussion on Sequencer Serial port patches submitted by Cyril Chemparathy which will be useful background for you. That device has a similar concept where in some microcode downloaded into it can turn it into an I2C/SPI/GPIO or other device. Thanks, Sekhar > > > Kevin > > > --- > > arch/arm/mach-davinci/include/mach/pru/omapl_pru.h | 44 > ++++ > > .../mach-davinci/include/mach/pru/omapl_prucore.h | 137 > +++++++++++ > > arch/arm/mach-davinci/include/mach/pru/pru.h | 100 > ++++++++ > > arch/arm/mach-davinci/pru.c | 237 > ++++++++++++++++++++ > > 4 files changed, 518 insertions(+), 0 deletions(-) > > create mode 100644 > arch/arm/mach-davinci/include/mach/pru/omapl_pru.h > > create mode 100644 > arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h > > create mode 100644 > arch/arm/mach-davinci/include/mach/pru/pru.h > > create mode 100644 arch/arm/mach-davinci/pru.c > > > > > diff --git > a/arch/arm/mach-davinci/include/mach/pru/omapl_pru.h > b/arch/arm/mach-davinci/include/mach/pru/omapl_pru.h > > new file mode 100644 > > index 0000000..52b10e8 > > --- /dev/null > > +++ b/arch/arm/mach-davinci/include/mach/pru/omapl_pru.h > > @@ -0,0 +1,44 @@ > > +/* > > + * Copyright (C) 2010 Texas Instruments Incorporated > > + * Author: Jitendra Kumar <[email protected]> > > + * > > > + * This program is free software; you can redistribute it > and/or modify it > > + * under the terms of the GNU General Public License as > published by the > > + * Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY > of any kind, > > + * whether express or implied; without even the implied > warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See > the GNU > > + * General Public License for more details. > > + */ > > + > > +#ifndef _OMAPL_PRU_H_ > > +#define _OMAPL_PRU_H_ > > + > > +#define OMAPL_PRU_FMK(PER_REG_FIELD, val) > \ > > + (((val) << OMAPL_##PER_REG_FIELD##_SHIFT) & > OMAPL_##PER_REG_FIELD##_MASK) > > + > > +#define OMAPL_PRU_FEXT(reg, PER_REG_FIELD) > \ > > + (((reg) & OMAPL_##PER_REG_FIELD##_MASK) >> > OMAPL_##PER_REG_FIELD##_SHIFT) > > + > > +#define OMAPL_PRU_FINS(reg, PER_REG_FIELD, val) > \ > > + ((reg) = ((reg) & ~OMAPL_##PER_REG_FIELD##_MASK) > \ > > + | OMAPL_PRU_FMK(PER_REG_FIELD, val)) > > + > > +#define OMAPL_PRU_FMKT(PER_REG_FIELD, TOKEN) > \ > > + OMAPL_PRU_FMK(PER_REG_FIELD, > OMAPL_##PER_REG_FIELD##_##TOKEN) > > + > > +#define OMAPL_PRU_FINST(reg, PER_REG_FIELD, TOKEN) > \ > > + OMAPL_PRU_FINS((reg), PER_REG_FIELD, > OMAPL_##PER_REG_FIELD##_##TOKEN) > > + > > +#define OMAPL_PRU_FMKR(msb, lsb, val) > \ > > + (((val) & ((1 << ((msb) - (lsb) + 1)) - 1)) << (lsb)) > > + > > +#define OMAPL_PRU_FEXTR(reg, msb, lsb) > \ > > + (((reg) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1)) > > + > > +#define OMAPL_PRU_FINSR(reg, msb, lsb, val) > \ > > + ((reg) = ((reg) & ~(((1 << ((msb) - (lsb) + 1)) - 1) << > (lsb))) \ > > + | OMAPL_PRU_FMKR(msb, lsb, val)) > > + > > +#endif /* _OMAPL_PRU_H_ */ > > diff --git > a/arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h > b/arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h > > new file mode 100644 > > index 0000000..cf43b1f > > --- /dev/null > > +++ b/arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h > > @@ -0,0 +1,137 @@ > > > +/* > > + * Copyright (C) 2010 Texas Instruments Incorporated > > + * Author: Jitendra Kumar <[email protected]> > > + * > > > + * This program is free software; you can redistribute it > and/or modify it > > + * under the terms of the GNU General Public License as > published by the > > + * Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY > of any kind, > > + * whether express or implied; without even the implied > warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See > the GNU > > + * General Public License for more details. > > + */ > > + > > +#ifndef _OMAPL_PRUCORE_H_ > > +#define _OMAPL_PRUCORE_H_ > > + > > +#include <linux/types.h> > > +#include <mach/pru/omapl_pru.h> > > + > > +#define OMAPL_PRUCORE_0 (0) > > +#define OMAPL_PRUCORE_1 (1) > > + > > +#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_MASK > (0xFFFF0000u) > > +#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_SHIFT > (0x00000010u) > > +#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_MASK > (0x00008000u) > > +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_SHIFT > (0x0000000Fu) > > +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_HALT > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_RUN > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_MASK > (0x00000100u) > > +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_SHIFT > (0x00000008u) > > +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_FREERUN > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_SINGLE > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_MASK > (0x00000008u) > > +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_SHIFT > (0x00000003u) > > +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_DISABLE > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_ENABLE > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_SLEEPING_MASK > (0x00000004u) > > +#define OMAPL_PRUCORE_CONTROL_SLEEPING_SHIFT > (0x00000002u) > > +#define OMAPL_PRUCORE_CONTROL_SLEEPING_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SLEEPING_NOTASLEEP > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SLEEPING_ASLEEP > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_ENABLE_MASK > (0x00000002u) > > +#define OMAPL_PRUCORE_CONTROL_ENABLE_SHIFT > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_ENABLE_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_ENABLE_DISABLE > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_ENABLE_ENABLE > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_MASK > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_SHIFT > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_RESETVAL > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_RESET > (0x00000000u) > > +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_OUT_OF_RESET > (0x00000001u) > > +#define OMAPL_PRUCORE_CONTROL_RESETVAL > (0x00000000u) > > + > > +typedef struct { > > + volatile u32 CONTROL; > > + volatile u32 STATUS; > > + volatile u32 WAKEUP; > > + volatile u32 CYCLECNT; > > + volatile u32 STALLCNT; > > + volatile u8 RSVD0[12]; > > + volatile u32 CONTABBLKIDX0; > > + volatile u32 CONTABBLKIDX1; > > + volatile u32 CONTABPROPTR0; > > + volatile u32 CONTABPROPTR1; > > + volatile u8 RSVD1[976]; > > + volatile u32 INTGPR0; > > + volatile u32 INTGPR1; > > + volatile u32 INTGPR2; > > + volatile u32 INTGPR3; > > + volatile u32 INTGPR4; > > + volatile u32 INTGPR5; > > + volatile u32 INTGPR6; > > + volatile u32 INTGPR7; > > + volatile u32 INTGPR8; > > + volatile u32 INTGPR9; > > + volatile u32 INTGPR10; > > + volatile u32 INTGPR11; > > + volatile u32 INTGPR12; > > + volatile u32 INTGPR13; > > + volatile u32 INTGPR14; > > + volatile u32 INTGPR15; > > + volatile u32 INTGPR16; > > + volatile u32 INTGPR17; > > + volatile u32 INTGPR18; > > + volatile u32 INTGPR19; > > + volatile u32 INTGPR20; > > + volatile u32 INTGPR21; > > + volatile u32 INTGPR22; > > + volatile u32 INTGPR23; > > + volatile u32 INTGPR24; > > + volatile u32 INTGPR25; > > + volatile u32 INTGPR26; > > + volatile u32 INTGPR27; > > + volatile u32 INTGPR28; > > + volatile u32 INTGPR29; > > + volatile u32 INTGPR30; > > + volatile u32 INTGPR31; > > + volatile u32 INTCTER0; > > + volatile u32 INTCTER1; > > + volatile u32 INTCTER2; > > + volatile u32 INTCTER3; > > + volatile u32 INTCTER4; > > + volatile u32 INTCTER5; > > + volatile u32 INTCTER6; > > + volatile u32 INTCTER7; > > + volatile u32 INTCTER8; > > + volatile u32 INTCTER9; > > + volatile u32 INTCTER10; > > + volatile u32 INTCTER11; > > + volatile u32 INTCTER12; > > + volatile u32 INTCTER13; > > + volatile u32 INTCTER14; > > + volatile u32 INTCTER15; > > + volatile u32 INTCTER16; > > + volatile u32 INTCTER17; > > + volatile u32 INTCTER18; > > + volatile u32 INTCTER19; > > + volatile u32 INTCTER20; > > + volatile u32 INTCTER21; > > + volatile u32 INTCTER22; > > + volatile u32 INTCTER23; > > + volatile u32 INTCTER24; > > + volatile u32 INTCTER25; > > + volatile u32 INTCTER26; > > + volatile u32 INTCTER27; > > + volatile u32 INTCTER28; > > + volatile u32 INTCTER29; > > + volatile u32 INTCTER30; > > + volatile u32 INTCTER31; > > +} OMAPL_PrucoreRegs, *OMAPL_PrucoreRegsOvly; > > + > > +#endif > > diff --git a/arch/arm/mach-davinci/include/mach/pru/pru.h > b/arch/arm/mach-davinci/include/mach/pru/pru.h > > new file mode 100644 > > index 0000000..366b2dc > > --- /dev/null > > +++ b/arch/arm/mach-davinci/include/mach/pru/pru.h > > @@ -0,0 +1,100 @@ > > > +/* > > + * Copyright (C) 2010 Texas Instruments Incorporated > > + * Author: Jitendra Kumar <[email protected]> > > + * > > > + * This program is free software; you can redistribute it > and/or modify it > > + * under the terms of the GNU General Public License as > published by the > > + * Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY > of any kind, > > + * whether express or implied; without even the implied > warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See > the GNU > > + * General Public License for more details. > > + */ > > + > > +#ifndef _PRU_H_ > > +#define _PRU_H_ > > + > > +#include <linux/types.h> > > +#include "omapl_prucore.h" > > + > > +#define PRU_NUM0 OMAPL_PRUCORE_0 > > +#define PRU_NUM1 OMAPL_PRUCORE_1 > > + > > +#define PRU_PRU0_BASE_ADDRESS 0 > > +#define PRU_INTC_BASE_ADDRESS > (PRU_PRU0_BASE_ADDRESS + 0x4000) > > +#define PRU_INTC_GLBLEN > (PRU_INTC_BASE_ADDRESS + 0x10) > > +#define PRU_INTC_GLBLNSTLVL > (PRU_INTC_BASE_ADDRESS + 0x1C) > > +#define PRU_INTC_STATIDXSET > (PRU_INTC_BASE_ADDRESS + 0x20) > > +#define PRU_INTC_STATIDXCLR > (PRU_INTC_BASE_ADDRESS + 0x24) > > +#define PRU_INTC_ENIDXSET > (PRU_INTC_BASE_ADDRESS + 0x28) > > +#define PRU_INTC_ENIDXCLR > (PRU_INTC_BASE_ADDRESS + 0x2C) > > +#define PRU_INTC_HSTINTENIDXSET > (PRU_INTC_BASE_ADDRESS + 0x34) > > +#define PRU_INTC_HSTINTENIDXCLR > (PRU_INTC_BASE_ADDRESS + 0x38) > > +#define PRU_INTC_GLBLPRIIDX > (PRU_INTC_BASE_ADDRESS + 0x80) > > +#define PRU_INTC_STATSETINT0 > (PRU_INTC_BASE_ADDRESS + 0x200) > > +#define PRU_INTC_STATSETINT1 > (PRU_INTC_BASE_ADDRESS + 0x204) > > +#define PRU_INTC_STATCLRINT0 > (PRU_INTC_BASE_ADDRESS + 0x280) > > +#define PRU_INTC_STATCLRINT1 > (PRU_INTC_BASE_ADDRESS + 0x284) > > +#define PRU_INTC_ENABLESET0 > (PRU_INTC_BASE_ADDRESS + 0x300) > > +#define PRU_INTC_ENABLESET1 > (PRU_INTC_BASE_ADDRESS + 0x304) > > +#define PRU_INTC_ENABLECLR0 > (PRU_INTC_BASE_ADDRESS + 0x380) > > +#define PRU_INTC_ENABLECLR1 > (PRU_INTC_BASE_ADDRESS + 0x384) > > +#define PRU_INTC_CHANMAP0 > (PRU_INTC_BASE_ADDRESS + 0x400) > > +#define PRU_INTC_CHANMAP1 > (PRU_INTC_BASE_ADDRESS + 0x404) > > +#define PRU_INTC_CHANMAP2 > (PRU_INTC_BASE_ADDRESS + 0x408) > > +#define PRU_INTC_CHANMAP3 > (PRU_INTC_BASE_ADDRESS + 0x40C) > > +#define PRU_INTC_CHANMAP4 > (PRU_INTC_BASE_ADDRESS + 0x410) > > +#define PRU_INTC_CHANMAP5 > (PRU_INTC_BASE_ADDRESS + 0x414) > > +#define PRU_INTC_CHANMAP6 > (PRU_INTC_BASE_ADDRESS + 0x418) > > +#define PRU_INTC_CHANMAP7 > (PRU_INTC_BASE_ADDRESS + 0x41C) > > +#define PRU_INTC_CHANMAP8 > (PRU_INTC_BASE_ADDRESS + 0x420) > > +#define PRU_INTC_CHANMAP9 > (PRU_INTC_BASE_ADDRESS + 0x424) > > +#define PRU_INTC_CHANMAP10 > (PRU_INTC_BASE_ADDRESS + 0x428) > > +#define PRU_INTC_CHANMAP11 > (PRU_INTC_BASE_ADDRESS + 0x42C) > > +#define PRU_INTC_CHANMAP12 > (PRU_INTC_BASE_ADDRESS + 0x430) > > +#define PRU_INTC_CHANMAP13 > (PRU_INTC_BASE_ADDRESS + 0x434) > > +#define PRU_INTC_CHANMAP14 > (PRU_INTC_BASE_ADDRESS + 0x438) > > +#define PRU_INTC_CHANMAP15 > (PRU_INTC_BASE_ADDRESS + 0x43C) > > +#define PRU_INTC_HOSTMAP0 > (PRU_INTC_BASE_ADDRESS + 0x800) > > +#define PRU_INTC_HOSTMAP1 > (PRU_INTC_BASE_ADDRESS + 0x804) > > +#define PRU_INTC_HOSTMAP2 > (PRU_INTC_BASE_ADDRESS + 0x808) > > +#define PRU_INTC_POLARITY0 > (PRU_INTC_BASE_ADDRESS + 0xD00) > > +#define PRU_INTC_POLARITY1 > (PRU_INTC_BASE_ADDRESS + 0xD04) > > +#define PRU_INTC_TYPE0 > (PRU_INTC_BASE_ADDRESS + 0xD80) > > +#define PRU_INTC_TYPE1 > (PRU_INTC_BASE_ADDRESS + 0xD84) > > +#define PRU_INTC_HOSTINTEN > (PRU_INTC_BASE_ADDRESS + 0x1500) > > +#define PRU_INTC_HOSTINTLVL_MAX 9 > > + > > +typedef struct arm_pru_iomap { > > + void *pru_io_addr; > > + void *psc0_io_addr; > > + void *psc1_io_addr; > > + void *syscfg_io_addr; > > + u32 pru_clk_freq; > > +} arm_pru_iomap; > > + > > +u32 pru_enable(u8 pruNum, arm_pru_iomap *pru_arm_iomap); > > + > > +u32 pru_load(u8 pruNum, u32 *pruCode, u32 codeSizeInWords, > > + arm_pru_iomap *pru_arm_iomap); > > + > > +u32 pru_run(u8 pruNum, arm_pru_iomap *pru_arm_iomap); > > + > > +u32 pru_waitForHalt(u8 pruNum, s32 timeout, arm_pru_iomap > *pru_arm_iomap); > > + > > +u32 pru_disable(arm_pru_iomap *pru_arm_iomap); > > + > > +s16 pru_ram_write_data(u32 u32offset, u8 *pu8datatowrite, > > + u16 u16wordstowrite, arm_pru_iomap > *pru_arm_iomap); > > + > > +s16 pru_ram_read_data(u32 u32offset, u8 *pu8datatoread, > > + u16 u16wordstoread, arm_pru_iomap > *pru_arm_iomap); > > + > > +s16 pru_ram_read_data_4byte(u32 u32offset, u32 > *pu32datatoread, > > + s16 s16wordstoread); > > + > > +s16 pru_ram_write_data_4byte(u32 u32offset, u32 > *pu32datatoread, > > + s16 s16wordstoread); > > + > > +#endif /* End _PRU_H_ */ > > diff --git a/arch/arm/mach-davinci/pru.c > b/arch/arm/mach-davinci/pru.c > > new file mode 100644 > > index 0000000..0cd2561 > > --- /dev/null > > +++ b/arch/arm/mach-davinci/pru.c > > @@ -0,0 +1,237 @@ > > > +/* > > + * Copyright (C) 2010 Texas Instruments Incorporated > > + * Author: Jitendra Kumar <[email protected]> > > + * > > > + * This program is free software; you can redistribute it > and/or modify it > > + * under the terms of the GNU General Public License as > published by the > > + * Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY > of any kind, > > + * whether express or implied; without even the implied > warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See > the GNU > > + * General Public License for more details. > > + */ > > + > > +#include <linux/types.h> > > +#include <linux/module.h> > > +#include <asm-generic/errno-base.h> > > +#include <mach/pru/omapl_pru.h> > > +#include <mach/pru/omapl_prucore.h> > > +#include <mach/pru/pru.h> > > + > > +u32 pru_disable(arm_pru_iomap *pru_arm_iomap) > > +{ > > + OMAPL_PrucoreRegsOvly hPru; > > + > > + /* Disable PRU0 */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + 0x7000); > > + OMAPL_PRU_FINST(hPru->CONTROL, > PRUCORE_CONTROL_COUNTENABLE, DISABLE); > > + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, > DISABLE); > > + > > + /* Reset PRU0 */ > > + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; > > + > > + /* Disable PRU1 */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + 0x7800); > > + OMAPL_PRU_FINST(hPru->CONTROL, > PRUCORE_CONTROL_COUNTENABLE, DISABLE); > > + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, > DISABLE); > > + > > + /* Reset PRU1 */ > > + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; > > + > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_disable); > > + > > +u32 pru_enable(u8 pruNum, arm_pru_iomap *pru_arm_iomap) > > +{ > > + OMAPL_PrucoreRegsOvly hPru; > > + > > + if (pruNum == OMAPL_PRUCORE_0) { > > + /* Reset PRU0 */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + > 0x7000); > > + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; > > + } else if (pruNum == OMAPL_PRUCORE_1) { > > + /* Reset PRU1 */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + > 0x7800); > > + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; > > + } > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_enable); > > + > > +/* Load the specified PRU with code */ > > +u32 pru_load(u8 pruNum, u32 *pruCode, u32 codeSizeInWords, > > + arm_pru_iomap *pru_arm_iomap) > > +{ > > + u32 *pruIram; > > + u32 i; > > + > > + if (pruNum == OMAPL_PRUCORE_0) { > > + pruIram = (u32 *) ((u32) > pru_arm_iomap->pru_io_addr + 0x8000); > > + } else if (pruNum == OMAPL_PRUCORE_1) { > > + pruIram = (u32 *) ((u32) > pru_arm_iomap->pru_io_addr + 0xc000); > > + } else { > > + return -EIO; > > + } > > + > > + pru_enable(pruNum, pru_arm_iomap); > > + > > + /* Copy dMAX code to its instruction RAM */ > > + for (i = 0; i < codeSizeInWords; i++) { > > + pruIram[i] = pruCode[i]; > > + } > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_load); > > + > > +u32 pru_run(u8 pruNum, arm_pru_iomap *pru_arm_iomap) > > +{ > > + OMAPL_PrucoreRegsOvly hPru; > > + > > + if (pruNum == OMAPL_PRUCORE_0) { > > + /* OMAPL_PRUCORE_0_REGS; */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + > 0x7000); > > + } else if (pruNum == OMAPL_PRUCORE_1) { > > + /* OMAPL_PRUCORE_1_REGS; */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + > 0x7800); > > + } else { > > + return -EIO; > > + } > > + > > + /* Enable dMAX, let it execute the code we just copied > */ > > + OMAPL_PRU_FINST(hPru->CONTROL, > PRUCORE_CONTROL_COUNTENABLE, ENABLE); > > + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, > ENABLE); > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_run); > > + > > +u32 pru_waitForHalt(u8 pruNum, s32 timeout, arm_pru_iomap > *pru_arm_iomap) > > +{ > > + OMAPL_PrucoreRegsOvly hPru; > > + > > + s32 cnt = timeout; > > + > > + if (pruNum == OMAPL_PRUCORE_0) { > > + /* OMAPL_PRUCORE_0_REGS; */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + > 0x7000); > > + } else if (pruNum == OMAPL_PRUCORE_1) { > > + /* OMAPL_PRUCORE_1_REGS; */ > > + hPru = (OMAPL_PrucoreRegsOvly) > > + ((u32) pru_arm_iomap->pru_io_addr + > 0x7800); > > + } else { > > + return -EIO; > > + } > > + > > + while (OMAPL_PRU_FEXT(hPru->CONTROL, > PRUCORE_CONTROL_RUNSTATE) == > > + OMAPL_PRUCORE_CONTROL_RUNSTATE_RUN) { > > + if (cnt > 0) { > > + cnt--; > > + } > > + if (cnt == 0) { > > + return -EBUSY; > > + } > > + } > > + > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_waitForHalt); > > + > > +/* > > + * u32offset Offset of the data RAM where > > + * the data has to be written > > + * pu32datatowrite Pointer to a buffer that holds > > + * the data to be written into RAM > > + * u16wordstowrite Number of bytes to be written > into that RAM > > + * > > + * return SUCCESS or FAILURE > > + */ > > +s16 pru_ram_write_data(u32 u32offset, u8 *pu8datatowrite, > > + u16 u16bytestowrite, arm_pru_iomap > *pru_arm_iomap) > > +{ > > + u8 *pu8addresstowrite; > > + u16 u16loop; > > + u32offset = (u32)pru_arm_iomap->pru_io_addr + u32offset; > > + pu8addresstowrite = (u8 *) (u32offset); > > + > > + for (u16loop = 0; u16loop < u16bytestowrite; u16loop++) > > + *pu8addresstowrite++ = *pu8datatowrite++; > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_ram_write_data); > > + > > +/* > > + * param u32offset Offset of the data RAM where the > > + * data has to be read > > + * param pu8datatoread Pointer to a buffer that would > hold > > + * the data to be read from the RAM > > + * param u16bytestoread Number of bytes to be read from > RAM > > + * > > + * return SUCCESS or FAILURE > > + */ > > +s16 pru_ram_read_data(u32 u32offset, u8 *pu8datatoread, > > + u16 u16bytestoread, arm_pru_iomap > *pru_arm_iomap) > > +{ > > + u8 *pu8addresstoread; > > + u16 u16loop; > > + u32offset = (u32)pru_arm_iomap->pru_io_addr + u32offset; > > + pu8addresstoread = (u8 *) (u32offset); > > + > > + for (u16loop = 0; u16loop < u16bytestoread; u16loop++) > > + *pu8datatoread++ = *pu8addresstoread++; > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_ram_read_data); > > + > > +/* > > + * param u32offset Offset of the > data RAM where the > > + * data has to be written > > + * param pu32datatowrite Pointer to a buffer that > holds the > > + * data to be written into RAM > > + * param u16wordstowrite Number of words to be > written > > + * > > + * return SUCCESS or FAILURE > > + */ > > +s16 pru_ram_write_data_4byte(u32 u32offset, u32 > *pu32datatowrite, > > + s16 u16wordstowrite) > > +{ > > + u32 *pu32addresstowrite; > > + s16 u16loop; > > + > > + pu32addresstowrite = (u32 *)(u32offset); > > + > > + for (u16loop = 0; u16loop < u16wordstowrite; u16loop++) > > + *pu32addresstowrite++ = *pu32datatowrite++; > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_ram_write_data_4byte); > > + > > +/* > > + * param u32offset Offset of the > data RAM where the > > + * data has to be read > > + * param pu32datatoread Pointer to a buffer that > would hold the > > + * data to be read from the RAM > > + * param u16wordstoread Number of words to be > read from RAM > > + * > > + * return SUCCESS or FAILURE > > + */ > > +s16 pru_ram_read_data_4byte(u32 u32offset, u32 > *pu32datatoread, > > + s16 u16wordstoread) > > +{ > > + u32 *pu32addresstoread; > > + s16 u16loop; > > + > > + pu32addresstoread = (u32 *)(u32offset); > > + > > + for (u16loop = 0; u16loop < u16wordstoread; u16loop++) > > + *pu32datatoread++ = *pu32addresstoread++; > > + return 0; > > +} > > +EXPORT_SYMBOL(pru_ram_read_data_4byte); > > > > _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
