The clock tree for dm644x is defined using the new structure davinci_clk. The SoC specific code re-uses clk-fixed-rate, clk-divider and clk-mux drivers in addition to the davinci specific clk drivers, clk-davinci-pll and clk-davinci-psc. Macros are defined to define the various clocks in the SoC.
Signed-off-by: Murali Karicheri <[email protected]> diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 0755d46..fdacdbd 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -12,6 +12,14 @@ #include <linux/clk.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/platform_data/clk-davinci-pll.h> +#include <linux/platform_data/clk-davinci-psc.h> +#include <linux/platform_data/davinci-clock.h> +#include <mach/pll.h> +#endif #include <asm/mach/map.h> @@ -26,9 +34,16 @@ #include <mach/gpio-davinci.h> #include "davinci.h" -#include "clock.h" #include "mux.h" #include "asp.h" +#ifndef CONFIG_COMMON_CLK +#include "clock.h" +#else +#define PLLM 0x110 +#define PREDIV 0x114 +#define POSTDIV 0x128 +#define PLLM_PLLM_MASK 0xff +#endif /* * Device specific clocks @@ -42,6 +57,7 @@ #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 +#ifndef CONFIG_COMMON_CLK static struct pll_data pll1_data = { .num = 1, .phys_base = DAVINCI_PLL1_BASE, @@ -324,6 +340,258 @@ static struct clk_lookup dm644x_clks[] = { CLK("watchdog", NULL, &timer2_clk), CLK(NULL, NULL, NULL), }; +#else +static struct clk_davinci_pll_data pll1_data = { + .phy_pllm = DAVINCI_PLL1_BASE + PLLM, + .phy_prediv = DAVINCI_PLL1_BASE + PREDIV, + .phy_postdiv = DAVINCI_PLL1_BASE + POSTDIV, + .pllm_mask = PLLM_PLLM_MASK, + .prediv_mask = PLLDIV_RATIO_MASK, + .postdiv_mask = PLLDIV_RATIO_MASK, + .num = 1, +}; + +static struct clk_fixed_data clkin_data = { + .rate = DM644X_REF_FREQ, + .flags = CLK_IS_ROOT, +}; + +static struct davinci_clk ref_clk_clkin = { + .name = "clkin", + .ref_clk_data = &clkin_data, +}; + +static struct clk_fixed_data oscin_data = { + .rate = DM644X_REF_FREQ, + .flags = CLK_IS_ROOT, +}; + +static struct davinci_clk ref_clk_oscin = { + .name = "oscin", + .ref_clk_data = &oscin_data, +}; + +static const char *ref_clk_mux_parents[] = {"clkin", "oscin"}; + +static struct clk_mux_data ref_clk_mux_data = { + .shift = PLLCTL_CLKMODE_SHIFT, + .width = PLLCTL_CLKMODE_WIDTH, + .num_parents = ARRAY_SIZE(ref_clk_mux_parents), + .parents = ref_clk_mux_parents, + .phys_base = DAVINCI_PLL1_BASE + PLLCTL, +}; + +static struct davinci_clk ref_clk_mux = { + .name = "ref_clk_mux", + .parent = &ref_clk_clkin, + .mux_data = &ref_clk_mux_data, +}; + +static struct davinci_clk pll1_clk = { + .name = "pll1", + .pll_type = DAVINCI_MAIN_PLL, + .parent = &ref_clk_mux, + .pll_data = { + .davinci = &pll1_data, + }, +}; + +static const char *pll1_plldiv_clk_mux_parents[] = { + "ref_clk_mux", "pll1"}; + +static struct clk_mux_data pll1_plldiv_clk_mux_data = { + .shift = PLLCTL_PLLEN_SHIFT, + .width = PLLCTL_PLLEN_WIDTH, + .num_parents = ARRAY_SIZE(pll1_plldiv_clk_mux_parents), + .parents = pll1_plldiv_clk_mux_parents, + .phys_base = DAVINCI_PLL1_BASE + PLLCTL, +}; + +static struct davinci_clk pll1_plldiv_clk_mux = { + .name = "pll1_plldiv_clk_mux", + .parent = &pll1_clk, + .mux_data = &pll1_plldiv_clk_mux_data, +}; + +#define define_pll1_div_clk(__pll, __div, __name) \ + static struct clk_divider_data pll1_div_data##__div = { \ + .div_reg = DAVINCI_PLL1_BASE + PLLDIV##__div, \ + .width = 5, \ + }; \ + \ + static struct davinci_clk __name = { \ + .name = #__name, \ + .parent = &__pll, \ + .pll_div_data = &pll1_div_data##__div, \ + } + +define_pll1_div_clk(pll1_plldiv_clk_mux, 1, pll1_sysclk1); +define_pll1_div_clk(pll1_plldiv_clk_mux, 2, pll1_sysclk2); +define_pll1_div_clk(pll1_plldiv_clk_mux, 3, pll1_sysclk3); +define_pll1_div_clk(pll1_plldiv_clk_mux, 4, pll1_sysclk4); +define_pll1_div_clk(pll1_plldiv_clk_mux, 5, pll1_sysclk5); + +static struct clk_divider_data pll1_sysclkbp_data = { + .div_reg = BPDIV, +}; + +static struct davinci_clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &ref_clk_mux, + .pll_div_data = &pll1_sysclkbp_data, +}; + +static struct clk_davinci_pll_data pll2_data = { + .phy_pllm = DAVINCI_PLL2_BASE + PLLM, + .phy_prediv = DAVINCI_PLL2_BASE + PREDIV, + .phy_postdiv = DAVINCI_PLL2_BASE + POSTDIV, + .pllm_mask = PLLM_PLLM_MASK, + .prediv_mask = PLLDIV_RATIO_MASK, + .postdiv_mask = PLLDIV_RATIO_MASK, + .num = 2, +}; + +static struct davinci_clk pll2_clk = { + .name = "pll2", + .pll_type = DAVINCI_MAIN_PLL, + .parent = &ref_clk_mux, + .pll_data = { + .davinci = &pll2_data, + }, +}; + +#define define_pll2_div_clk(__pll, __div, __name) \ + static struct clk_divider_data pll2_div_data##__div = { \ + .div_reg = DAVINCI_PLL2_BASE + PLLDIV##__div, \ + .width = 5, \ + }; \ + \ + static struct davinci_clk __name = { \ + .name = #__name, \ + .parent = &__pll, \ + .pll_div_data = &pll2_div_data##__div, \ + } + +static const char *pll2_plldiv_clk_mux_parents[] = { + "ref_clk_mux", "pll2"}; + +static struct clk_mux_data pll2_plldiv_clk_mux_data = { + .shift = PLLCTL_PLLEN_SHIFT, + .width = PLLCTL_PLLEN_WIDTH, + .num_parents = ARRAY_SIZE(pll2_plldiv_clk_mux_parents), + .parents = pll2_plldiv_clk_mux_parents, + .phys_base = DAVINCI_PLL2_BASE + PLLCTL, +}; + +static struct davinci_clk pll2_plldiv_clk_mux = { + .name = "pll2_plldiv_clk_mux", + .parent = &pll2_clk, + .mux_data = &pll2_plldiv_clk_mux_data, +}; + +define_pll2_div_clk(pll2_plldiv_clk_mux, 1, pll2_sysclk1); +define_pll2_div_clk(pll2_plldiv_clk_mux, 2, pll2_sysclk2); + +struct clk_divider_data pll2_sysclkbp_data = { + .div_reg = DAVINCI_PLL2_BASE + BPDIV, + .width = 5, +}; + +static struct davinci_clk pll2_sysclkbp = { + .name = "pll2_sysclkbp", + .parent = &ref_clk_mux, + .pll_div_data = &pll2_sysclkbp_data, +}; + +#define __lpsc_clk(cname, _parent, mod, flgs, _flgs, dom) \ + static struct clk_davinci_psc_data clk_psc_data##cname = { \ + .domain = DAVINCI_GPSC_##dom, \ + .lpsc = DAVINCI_LPSC_##mod, \ + .flags = flgs, \ + }; \ + \ + static struct davinci_clk clk_##cname = { \ + .name = #cname, \ + .parent = &_parent, \ + .flags = _flgs, \ + .psc_data = &clk_psc_data##cname \ + } + +#define lpsc_clk_enabled(cname, parent, mod) \ + __lpsc_clk(cname, parent, mod, 0, ALWAYS_ENABLED, ARMDOMAIN) + +#define lpsc_clk(cname, flgs, parent, mod, dom) \ + __lpsc_clk(cname, parent, mod, flgs, 0, dom) + +lpsc_clk_enabled(arm, pll1_sysclk2, ARM); +lpsc_clk(dsp, CLK_IGNORE_UNUSED, pll1_sysclk1, GEM, DSPDOMAIN); +lpsc_clk(vicp, CLK_IGNORE_UNUSED, pll1_sysclk2, IMCOP, DSPDOMAIN); +lpsc_clk(vpss_master, 0, pll1_sysclk3, VPSSMSTR, ARMDOMAIN); +lpsc_clk(vpss_slave, 0, pll1_sysclk3, VPSSSLV, ARMDOMAIN); +lpsc_clk(uart0, 0, ref_clk_mux, UART0, ARMDOMAIN); +lpsc_clk(uart1, 0, ref_clk_mux, UART1, ARMDOMAIN); +lpsc_clk(uart2, 0, ref_clk_mux, UART2, ARMDOMAIN); +lpsc_clk(emac, 0, pll1_sysclk5, EMAC_WRAPPER, ARMDOMAIN); +lpsc_clk(i2c, 0, ref_clk_mux, I2C, ARMDOMAIN); +lpsc_clk(ide, 0, pll1_sysclk5, ATA, ARMDOMAIN); +lpsc_clk(asp0, 0, pll1_sysclk5, McBSP, ARMDOMAIN); +lpsc_clk(mmcsd, 0, pll1_sysclk5, MMC_SD, ARMDOMAIN); +lpsc_clk(spi, 0, pll1_sysclk5, SPI, ARMDOMAIN); +lpsc_clk(gpio, 0, pll1_sysclk5, GPIO, ARMDOMAIN); +lpsc_clk(usb, 0, pll1_sysclk5, USB, ARMDOMAIN); +lpsc_clk(vlynq, 0, pll1_sysclk5, VLYNQ, ARMDOMAIN); +lpsc_clk(aemif, 0, pll1_sysclk5, AEMIF, ARMDOMAIN); +lpsc_clk(pwm0, 0, ref_clk_mux, PWM0, ARMDOMAIN); +lpsc_clk(pwm1, 0, ref_clk_mux, PWM1, ARMDOMAIN); +lpsc_clk(pwm2, 0, ref_clk_mux, PWM2, ARMDOMAIN); +lpsc_clk(timer0, 0, ref_clk_mux, TIMER0, ARMDOMAIN); +lpsc_clk(timer1, 0, ref_clk_mux, TIMER1, ARMDOMAIN); +lpsc_clk(timer2, CLK_IGNORE_UNUSED, ref_clk_mux, TIMER2, ARMDOMAIN); + +static struct davinci_clk_lookup dm644x_clks[] = { + CLK(NULL, "clkin", &ref_clk_clkin), + CLK(NULL, "oscin", &ref_clk_oscin), + CLK(NULL, "ref_clk_mux", &ref_clk_mux), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_plldiv_clk_mux", &pll1_plldiv_clk_mux), + CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_plldiv_clk_mux", &pll2_plldiv_clk_mux), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), + CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), + CLK(NULL, "dsp", &clk_dsp), + CLK(NULL, "arm", &clk_arm), + CLK(NULL, "vicp", &clk_vicp), + CLK(NULL, "vpss_master", &clk_vpss_master), + CLK(NULL, "vpss_slave", &clk_vpss_slave), + CLK(NULL, "uart0", &clk_uart0), + CLK(NULL, "uart1", &clk_uart1), + CLK(NULL, "uart2", &clk_uart2), + CLK("davinci_emac.1", NULL, &clk_emac), + CLK("i2c_davinci.1", NULL, &clk_i2c), + CLK("palm_bk3710", NULL, &clk_ide), + CLK("davinci-mcbsp", NULL, &clk_asp0), + CLK("davinci_mmc.0", NULL, &clk_mmcsd), + CLK(NULL, "spi", &clk_spi), + CLK(NULL, "gpio", &clk_gpio), + CLK(NULL, "usb", &clk_usb), + CLK(NULL, "vlynq", &clk_vlynq), + CLK(NULL, "aemif", &clk_aemif), + CLK(NULL, "pwm0", &clk_pwm0), + CLK(NULL, "pwm1", &clk_pwm1), + CLK(NULL, "pwm2", &clk_pwm2), + CLK(NULL, "timer0", &clk_timer0), + CLK(NULL, "timer1", &clk_timer1), + CLK("watchdog", NULL, &clk_timer2), + CLK(NULL, NULL, NULL), +}; +#endif static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, @@ -873,6 +1141,32 @@ static struct platform_device dm644x_serial_device = { }, }; +#ifdef CONFIG_COMMON_CLK +struct clk_lookup vpss_master_lookups[] = { + { .dev_id = "dm644x_ccdc", .con_id = "master", }, +}; + +struct clk_lookup vpss_slave_lookups[] = { + { .dev_id = "dm644x_ccdc", .con_id = "slave", }, +}; + +static struct davinci_dev_lookup dev_clk_lookups[] = { + { + .con_id = "vpss_master", + .num_devs = ARRAY_SIZE(vpss_master_lookups), + .lookups = vpss_master_lookups, + }, + { + .con_id = "vpss_slave", + .num_devs = ARRAY_SIZE(vpss_slave_lookups), + .lookups = vpss_slave_lookups, + }, + { + .con_id = NULL, + }, +}; +#endif + static struct davinci_soc_info davinci_soc_info_dm644x = { .io_desc = dm644x_io_desc, .io_desc_num = ARRAY_SIZE(dm644x_io_desc), @@ -880,6 +1174,9 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .ids = dm644x_ids, .ids_num = ARRAY_SIZE(dm644x_ids), .cpu_clks = dm644x_clks, +#ifdef CONFIG_COMMON_CLK + .dev_clk_lookups = dev_clk_lookups, +#endif .psc_bases = dm644x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, @@ -923,11 +1220,13 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, dm644x_vpfe_dev.dev.platform_data = vpfe_cfg; platform_device_register(&dm644x_ccdc_dev); platform_device_register(&dm644x_vpfe_dev); +#ifndef CONFIG_COMMON_CLK /* Add ccdc clock aliases */ clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); +#endif } if (vpbe_cfg) { -- 1.7.9.5 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
