> All bulk endpoint transfers are sheduled using the single MUSB EP 1,
> AFAIR.
>>> 2. Is there a software work around ("Interrupt endpoint scheduling")
>>> that works with devices that need Interrupt EPs? If so what kernel
>>> version do I need?
>
>> "Interrupt endpoint scheduling" was implemented for very early v2.6.10
>> based MV kernels that TI used to ship. Recently Ravi up-ported that to
>> v3.3 but was only tested it on DA850 as per my knowledge. Here is the
>> link:
>> http://arago-project.org/git/projects/?p=linux-
davinci.git;a=commit;h=0795c14aa91650d778a27fe7b2ef23e2d9ff8c89
>
> This code seems to have the same mistake I fixed for 2.6.18 MV
> release --
> it tries to schedule several URBs concurrently on the same endpoint. It
> seems TI engineers have learned nothing from my work. :-(
I will wait for Ravi's reply if the "Interrupt endpoint scheduling was
tested for the DM6446 or if there is some type of implementation issue.
This patch was verified only on da830, not verified on DM6446. Did you
checked with this patch and face any issue. Can you list out totally how
many tx/rx bulk/interrupt pipes used? The limitation is only 4 Tx/Rx eps
is available.
This patch will help, if you can connect more interrupt devices (like HID
devices) but connecting devices which uses more bulk pipes could be
limitation.
1. Is Sergei's comment incorrect or am I not understanding?
"All bulk endpoint transfers are sheduled using the single MUSB EP 1,
AFAIR."
2. Here is the output of: cat /proc/bus/usb/devices It consists of the
DM6446 USB, TUSB2046B, and 2 usbnet devices.
T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 1
B: Alloc= 0/800 us ( 0%), #Int= 0, #Iso= 0
D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=01 MxPS=64 #Cfgs= 1
P: Vendor=1d6b ProdID=0002 Rev= 3.00
S: Manufacturer=Linux 3.0.0+ musb-hcd
S: Product=MUSB HDRC host driver
S: SerialNumber=musb-hdrc
C:* #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr= 0mA
I:* If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub
E: Ad=81(I) Atr=03(Int.) MxPS= 4 Ivl=256ms
T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=12 MxCh= 4
D: Ver= 1.10 Cls=09(hub ) Sub=00 Prot=00 MxPS= 8 #Cfgs= 1
P: Vendor=0451 ProdID=2046 Rev= 1.25
C:* #Ifs= 1 Cfg#= 1 Atr=e0 MxPwr= 0mA
I:* If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub
E: Ad=81(I) Atr=03(Int.) MxPS= 1 Ivl=255ms
T: Bus=01 Lev=02 Prnt=02 Port=00 Cnt=01 Dev#= 3 Spd=12 MxCh= 0
D: Ver= 2.00 Cls=02(comm.) Sub=00 Prot=00 MxPS=64 #Cfgs= 2
P: (Removed)
S: (Removed)
S: (Removed)
C: #Ifs= 2 Cfg#= 2 Atr=c0 MxPwr= 2mA
A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00
I: If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=
E: Ad=82(I) Atr=03(Int.) MxPS= 8 Ivl=32ms
I: If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=
E: Ad=81(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms
E: Ad=01(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms
C:* #Ifs= 2 Cfg#= 1 Atr=c0 MxPwr= 2mA
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=cdc_ether
E: Ad=82(I) Atr=03(Int.) MxPS= 16 Ivl=32ms
I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
E: Ad=81(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms
E: Ad=01(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms
T: Bus=01 Lev=02 Prnt=02 Port=01 Cnt=02 Dev#= 4 Spd=12 MxCh= 0
D: Ver= 2.00 Cls=02(comm.) Sub=00 Prot=00 MxPS=64 #Cfgs= 2
P: (Removed)
S: (Removed)
S: (Removed)
C: #Ifs= 2 Cfg#= 2 Atr=c0 MxPwr= 2mA
A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00
I: If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=
E: Ad=82(I) Atr=03(Int.) MxPS= 8 Ivl=32ms
I: If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=
E: Ad=81(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms
E: Ad=01(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms
C:* #Ifs= 2 Cfg#= 1 Atr=c0 MxPwr= 2mA
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=cdc_ether
E: Ad=82(I) Atr=03(Int.) MxPS= 16 Ivl=32ms
I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
E: Ad=81(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms
E: Ad=01(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms
3. Is there anyway to get this configuration to work correctly with the
DM6446?
Thanks,
Danny
_______________________________________________
Davinci-linux-open-source mailing list
[email protected]
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source