Package: openlibm
Version: 0.5.4+dfsg-2
Severity: important
Tags: sid + patch
Justification: FTBFS
User: debian-m...@lists.debian.org
Usertags: mips-patch
Package openlibm_0.5.4+dfsg-2 FTBFS on mips, mipsel, mips64el with following
error:
> make[1]: Entering directory '/«BUILDDIR»/openlibm-0.5.4+dfsg'
> Makefile:20: mips/Make.files: No such file or directory
> make[1]: *** No rule to make target 'mips/Make.files'. Stop.
> make[1]: Leaving directory '/«BUILDDIR»/openlibm-0.5.4+dfsg'
> dh_auto_clean: make -j2 distclean returned exit code 2
> debian/rules:6: recipe for target 'clean' failed
> make: *** [clean] Error 2
> dpkg-buildpackage: error: fakeroot debian/rules clean gave error exit status 2
Full build log:
https://buildd.debian.org/status/fetch.php?pkg=openlibm&arch=mips&ver=0.5.4%2Bdfsg-2&stamp=1484767295&raw=0
Build fails because there is no support for mips architectures.
I added all the necessary changes that are needed.
Code for files openlibm_fenv_mips.h, mips_fpmath.h and fenv.c was taken from
https://github.com/freebsd/freebsd
It was also necessary to change libopenlibm2.symbols file, to update the
missing symbols for mips arches.
I have created and attached patches that include these changes and resolve
these issues.
Patch add-mips-support.patch adds support for mips architectures.
Patch update-mips-symbols.patch update symbols for mips architectures.
With these patches package builds successfully on mips, mipsel, mips64el.
Regards,
Radovan
--- openlibm-0.5.4+dfsg_orig/debian/libopenlibm2.symbols 2017-01-24 08:51:29.000000000 +0000
+++ openlibm-0.5.4+dfsg/debian/libopenlibm2.symbols 2017-01-24 09:51:16.000000000 +0000
@@ -1,20 +1,20 @@
libopenlibm.so.2 libopenlibm2 #MINVER#
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_aT@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_atanhi@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_atanlo@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS0@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS1@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS2@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS3@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS4@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS5@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pS6@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_pi_lo@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_qS1@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_qS2@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_qS3@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_qS4@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)_ItL_qS5@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_aT@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_atanhi@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_atanlo@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS0@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS1@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS2@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS3@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS4@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS5@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pS6@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_pi_lo@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_qS1@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_qS2@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_qS3@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_qS4@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)_ItL_qS5@Base 0.4
__exp__D@Base 0.4
__fe_dfl_env@Base 0.4
#MISSING: 0.5.0# (arch=!armhf)__fedisableexcept@Base 0.4
@@ -37,23 +37,23 @@ libopenlibm.so.2 libopenlibm2 #MINVER#
(arch=!armhf)__isnormall@Base 0.4
__kernel_cos@Base 0.4
__kernel_cosdf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)__kernel_cosl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)__kernel_cosl@Base 0.4
__kernel_rem_pio2@Base 0.4
__kernel_sin@Base 0.4
#MISSING: 0.5.0# __kernel_sincos@Base 0.4
#MISSING: 0.5.0# __kernel_sincosdf@Base 0.4
__kernel_sindf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)__kernel_sinl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)__kernel_sinl@Base 0.4
__kernel_tan@Base 0.4
__kernel_tandf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)__kernel_tanl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)__kernel_tanl@Base 0.4
__ldexp_cexp@Base 0.4
__ldexp_cexpf@Base 0.4
__ldexp_exp@Base 0.4
__ldexp_expf@Base 0.4
__log__D@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)__p1evll@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)__polevll@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)__p1evll@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)__polevll@Base 0.5.0
__scan_nan@Base 0.5.0
__signbit@Base 0.4
__signbitf@Base 0.4
@@ -64,172 +64,172 @@ libopenlibm.so.2 libopenlibm2 #MINVER#
acosf@Base 0.4
acosh@Base 0.4
acoshf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)acoshl@Base 0.5.0
- (arch=!arm64 !powerpc !ppc64el !ppc64)acosl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)acoshl@Base 0.5.0
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)acosl@Base 0.4
asin@Base 0.4
asinf@Base 0.4
asinh@Base 0.4
asinhf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)asinhl@Base 0.5.0
- (arch=!arm64 !powerpc !ppc64el !ppc64)asinl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)asinhl@Base 0.5.0
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)asinl@Base 0.4
atan2@Base 0.4
atan2f@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)atan2l@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)atan2l@Base 0.4
atan@Base 0.4
atanf@Base 0.4
atanh@Base 0.4
atanhf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)atanhl@Base 0.5.0
- (arch=!arm64 !powerpc !ppc64el !ppc64)atanl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)atanhl@Base 0.5.0
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)atanl@Base 0.4
cabs@Base 0.4
cabsf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)cabsl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)cabsl@Base 0.4
cacos@Base 0.5.0
cacosf@Base 0.5.0
cacosh@Base 0.5.0
cacoshf@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cacoshl@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cacosl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cacoshl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cacosl@Base 0.5.0
carg@Base 0.4
cargf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cargl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cargl@Base 0.4
casin@Base 0.5.0
casinf@Base 0.5.0
casinh@Base 0.5.0
casinhf@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)casinhl@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)casinl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)casinhl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)casinl@Base 0.5.0
catan@Base 0.5.0
catanf@Base 0.5.0
catanh@Base 0.5.0
catanhf@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)catanhl@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)catanl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)catanhl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)catanl@Base 0.5.0
cbrt@Base 0.4
cbrtf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cbrtl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cbrtl@Base 0.5.0
ccos@Base 0.4
ccosf@Base 0.4
ccosh@Base 0.4
ccoshf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)ccoshl@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)ccosl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)ccoshl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)ccosl@Base 0.5.0
ceil@Base 0.4
ceilf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)ceill@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)ceill@Base 0.4
cexp@Base 0.4
cexpf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cexpl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cexpl@Base 0.5.0
cimag@Base 0.4
cimagf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cimagl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cimagl@Base 0.4
clog@Base 0.5.0
clogf@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)clogl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)clogl@Base 0.5.0
conj@Base 0.4
conjf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)conjl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)conjl@Base 0.4
copysign@Base 0.4
copysignf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)copysignl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)copysignl@Base 0.4
cos@Base 0.4
cosf@Base 0.4
cosh@Base 0.4
coshf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)coshl@Base 0.5.0
- (arch=!arm64 !powerpc !ppc64el !ppc64)cosl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)coshl@Base 0.5.0
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)cosl@Base 0.4
cpow@Base 0.4
cpowf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cpowl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cpowl@Base 0.4
cproj@Base 0.4
cprojf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)cprojl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)cprojl@Base 0.4
creal@Base 0.4
crealf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)creall@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)creall@Base 0.4
csin@Base 0.4
csinf@Base 0.4
csinh@Base 0.4
csinhf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)csinhl@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)csinl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)csinhl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)csinl@Base 0.5.0
csqrt@Base 0.4
csqrtf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)csqrtl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)csqrtl@Base 0.4
ctan@Base 0.4
ctanf@Base 0.4
ctanh@Base 0.4
ctanhf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)ctanhl@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)ctanl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)ctanhl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)ctanl@Base 0.5.0
#MISSING: 0.5.0# drem@Base 0.4
#MISSING: 0.5.0# dremf@Base 0.4
erf@Base 0.4
erfc@Base 0.4
erfcf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)erfcl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)erfcl@Base 0.5.0
erff@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)erfl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)erfl@Base 0.5.0
exp2@Base 0.4
exp2f@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)exp2l@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)exp2l@Base 0.4
exp@Base 0.4
expf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)expl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)expl@Base 0.5.0
expm1@Base 0.4
expm1f@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)expm1l@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)expm1l@Base 0.5.0
fabs@Base 0.4
fabsf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)fabsl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)fabsl@Base 0.4
fdim@Base 0.4
fdimf@Base 0.4
fdiml@Base 0.4
- (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64)feclearexcept@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)fedisableexcept@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)feenableexcept@Base 0.4
+ (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64 mips mipsel mips64el)feclearexcept@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)fedisableexcept@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)feenableexcept@Base 0.4
fegetenv@Base 0.4
- (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64)fegetexceptflag@Base 0.4
- (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64)fegetround@Base 0.4
+ (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64 mips mipsel mips64el)fegetexceptflag@Base 0.4
+ (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64 mips mipsel mips64el)fegetround@Base 0.4
feholdexcept@Base 0.4
feraiseexcept@Base 0.4
- (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64)fesetenv@Base 0.4
+ (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64 mips mipsel mips64el)fesetenv@Base 0.4
fesetexceptflag@Base 0.4
- (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64)fesetround@Base 0.4
- (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64)fetestexcept@Base 0.4
+ (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64 mips mipsel mips64el)fesetround@Base 0.4
+ (arch=i386 kfreebsd-i386 hurd-i386 armhf arm64 powerpc ppc64el ppc64 mips mipsel mips64el)fetestexcept@Base 0.4
feupdateenv@Base 0.4
#MISSING: 0.5.0# finite@Base 0.4
#MISSING: 0.5.0# finitef@Base 0.4
floor@Base 0.4
floorf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)floorl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)floorl@Base 0.4
fma@Base 0.4
fmaf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)fmal@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)fmal@Base 0.4
fmax@Base 0.4
fmaxf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)fmaxl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)fmaxl@Base 0.4
fmin@Base 0.4
fminf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)fminl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)fminl@Base 0.4
fmod@Base 0.4
fmodf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)fmodl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)fmodl@Base 0.4
(arch=i386 kfreebsd-i386 hurd-i386)fpgetprec@Base 0.5.0
(arch=i386 kfreebsd-i386 hurd-i386)fpsetprec@Base 0.5.0
frexp@Base 0.4
frexpf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)frexpl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)frexpl@Base 0.4
#MISSING: 0.5.0# gamma@Base 0.4
#MISSING: 0.5.0# gamma_r@Base 0.4
#MISSING: 0.5.0# gammaf@Base 0.4
#MISSING: 0.5.0# gammaf_r@Base 0.4
hypot@Base 0.4
hypotf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)hypotl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)hypotl@Base 0.4
ilogb@Base 0.4
ilogbf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)ilogbl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)ilogbl@Base 0.4
isinf@Base 0.4
isinff@Base 0.4
isnan@Base 0.4
@@ -243,70 +243,70 @@ libopenlibm.so.2 libopenlibm2 #MINVER#
jnf@Base 0.4
ldexp@Base 0.4
ldexpf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)ldexpl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)ldexpl@Base 0.4
lgamma@Base 0.4
lgamma_r@Base 0.4
lgammaf@Base 0.4
lgammaf_r@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)lgammal@Base 0.5.0
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)lgammal_r@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)lgammal@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)lgammal_r@Base 0.5.0
llrint@Base 0.4
llrintf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)llrintl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)llrintl@Base 0.4
llround@Base 0.4
llroundf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)llroundl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)llroundl@Base 0.4
log10@Base 0.4
log10f@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)log10l@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)log10l@Base 0.5.0
log1p@Base 0.4
log1pf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)log1pl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)log1pl@Base 0.5.0
log2@Base 0.4
log2f@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)log2l@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)log2l@Base 0.5.0
log@Base 0.4
logb@Base 0.4
logbf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)logbl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)logbl@Base 0.4
logf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)logl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)logl@Base 0.5.0
lrint@Base 0.4
lrintf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)lrintl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)lrintl@Base 0.4
lround@Base 0.4
lroundf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)lroundl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)lroundl@Base 0.4
modf@Base 0.4
modff@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)modfl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)modfl@Base 0.4
nan@Base 0.4
nanf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)nanl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)nanl@Base 0.4
nearbyint@Base 0.4
nearbyintf@Base 0.4
#MISSING: 0.5.0# nearbyintl@Base 0.4
nextafter@Base 0.4
nextafterf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)nextafterl@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)nexttoward@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)nextafterl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)nexttoward@Base 0.4
(arch=!armhf)nexttowardf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)nexttowardl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)nexttowardl@Base 0.4
pow@Base 0.4
powf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)powl@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)powl@Base 0.5.0
remainder@Base 0.4
remainderf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)remainderl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)remainderl@Base 0.4
remquo@Base 0.4
remquof@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)remquol@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)remquol@Base 0.4
rint@Base 0.4
rintf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)rintl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)rintl@Base 0.4
round@Base 0.4
roundf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)roundl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)roundl@Base 0.4
#MISSING: 0.5.0# scalb@Base 0.4
#MISSING: 0.5.0# scalbf@Base 0.4
scalbln@Base 0.4
@@ -314,34 +314,34 @@ libopenlibm.so.2 libopenlibm2 #MINVER#
scalblnl@Base 0.4
scalbn@Base 0.4
scalbnf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)scalbnl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)scalbnl@Base 0.4
signgam@Base 0.4
#MISSING: 0.5.0# significand@Base 0.4
#MISSING: 0.5.0# significandf@Base 0.4
sin@Base 0.4
sincos@Base 0.4
sincosf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)sincosl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)sincosl@Base 0.4
sinf@Base 0.4
sinh@Base 0.4
sinhf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)sinhl@Base 0.5.0
- (arch=!arm64 !powerpc !ppc64el !ppc64)sinl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)sinhl@Base 0.5.0
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)sinl@Base 0.4
sqrt@Base 0.4
sqrtf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)sqrtl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)sqrtl@Base 0.4
tan@Base 0.4
tanf@Base 0.4
tanh@Base 0.4
tanhf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)tanhl@Base 0.5.0
- (arch=!arm64 !powerpc !ppc64el !ppc64)tanl@Base 0.4
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)tanhl@Base 0.5.0
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)tanl@Base 0.4
tgamma@Base 0.4
tgammaf@Base 0.4
- (arch=!armhf !arm64 !powerpc !ppc64el !ppc64)tgammal@Base 0.5.0
+ (arch=!armhf !arm64 !powerpc !ppc64el !ppc64 !mips !mipsel !mips64el)tgammal@Base 0.5.0
trunc@Base 0.4
truncf@Base 0.4
- (arch=!arm64 !powerpc !ppc64el !ppc64)truncl@Base 0.4
+ (arch=!arm64 !powerpc !ppc64el !ppc64 !mips64el)truncl@Base 0.4
y0@Base 0.4
y0f@Base 0.4
y1@Base 0.4
--- openlibm-0.5.4+dfsg.orig/Make.inc
+++ openlibm-0.5.4+dfsg/Make.inc
@@ -92,6 +92,10 @@ ifeq ($(ARCH),x86_64)
override ARCH := amd64
endif
+ifeq ($(findstring mips,$(ARCH)),mips)
+override ARCH := mips
+endif
+
# If CFLAGS does not contain a -O optimization flag, default to -O3
ifeq ($(findstring -O,$(CFLAGS)),)
CFLAGS_add += -O3
--- openlibm-0.5.4+dfsg.orig/Makefile
+++ openlibm-0.5.4+dfsg/Makefile
@@ -4,9 +4,11 @@ include ./Make.inc
SUBDIRS = src $(ARCH) bsdsrc
ifneq ($(ARCH), arm)
ifneq ($(ARCH), powerpc)
+ifneq ($(ARCH), mips)
SUBDIRS += ld80
endif
endif
+endif
define INC_template
TEST=test
--- openlibm-0.5.4+dfsg.orig/include/openlibm_fenv.h
+++ openlibm-0.5.4+dfsg/include/openlibm_fenv.h
@@ -10,6 +10,8 @@
#include <openlibm_fenv_i387.h>
#elif defined(__powerpc__)
#include <openlibm_fenv_powerpc.h>
+#elif defined(__mips__)
+#include <openlibm_fenv_mips.h>
#else
#error "Unsupported platform"
#endif
--- /dev/null
+++ openlibm-0.5.4+dfsg/include/openlibm_fenv_mips.h
@@ -0,0 +1,277 @@
+/*-
+ * Copyright (c) 2004-2005 David Schultz <d...@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _FENV_H_
+#define _FENV_H_
+
+#include <sys/types.h>
+
+#ifndef __fenv_static
+#define __fenv_static static
+#endif
+
+typedef __uint32_t fenv_t;
+typedef __uint32_t fexcept_t;
+
+/* Exception flags */
+#ifdef SOFTFLOAT
+#define _FPUSW_SHIFT 16
+#define FE_INVALID 0x0001
+#define FE_DIVBYZERO 0x0002
+#define FE_OVERFLOW 0x0004
+#define FE_UNDERFLOW 0x0008
+#define FE_INEXACT 0x0010
+#else
+#define _FCSR_CAUSE_SHIFT 10
+#define FE_INVALID 0x0040
+#define FE_DIVBYZERO 0x0020
+#define FE_OVERFLOW 0x0010
+#define FE_UNDERFLOW 0x0008
+#define FE_INEXACT 0x0004
+#endif
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
+ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+
+/* Rounding modes */
+#define FE_TONEAREST 0x0000
+#define FE_TOWARDZERO 0x0001
+#define FE_UPWARD 0x0002
+#define FE_DOWNWARD 0x0003
+#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
+ FE_UPWARD | FE_TOWARDZERO)
+__BEGIN_DECLS
+
+/* Default floating-point environment */
+extern const fenv_t __fe_dfl_env;
+#define FE_DFL_ENV (&__fe_dfl_env)
+
+/* We need to be able to map status flag positions to mask flag positions */
+#define _ENABLE_SHIFT 5
+#define _ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)
+
+#ifndef SOFTFLOAT
+#define __cfc1(__fcsr) __asm __volatile("cfc1 %0, $31" : "=r" (__fcsr))
+#define __ctc1(__fcsr) __asm __volatile("ctc1 %0, $31" :: "r" (__fcsr))
+#endif
+
+#ifdef SOFTFLOAT
+int feclearexcept(int __excepts);
+int fegetexceptflag(fexcept_t *__flagp, int __excepts);
+int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
+int feraiseexcept(int __excepts);
+int fetestexcept(int __excepts);
+int fegetround(void);
+int fesetround(int __round);
+int fegetenv(fenv_t *__envp);
+int feholdexcept(fenv_t *__envp);
+int fesetenv(const fenv_t *__envp);
+int feupdateenv(const fenv_t *__envp);
+#else
+__fenv_static inline int
+feclearexcept(int __excepts)
+{
+ fexcept_t fcsr;
+
+ __excepts &= FE_ALL_EXCEPT;
+ __cfc1(fcsr);
+ fcsr &= ~(__excepts | (__excepts << _FCSR_CAUSE_SHIFT));
+ __ctc1(fcsr);
+
+ return (0);
+}
+
+__fenv_static inline int
+fegetexceptflag(fexcept_t *__flagp, int __excepts)
+{
+ fexcept_t fcsr;
+
+ __excepts &= FE_ALL_EXCEPT;
+ __cfc1(fcsr);
+ *__flagp = fcsr & __excepts;
+
+ return (0);
+}
+
+__fenv_static inline int
+fesetexceptflag(const fexcept_t *__flagp, int __excepts)
+{
+ fexcept_t fcsr;
+
+ __excepts &= FE_ALL_EXCEPT;
+ __cfc1(fcsr);
+ fcsr &= ~__excepts;
+ fcsr |= *__flagp & __excepts;
+ __ctc1(fcsr);
+
+ return (0);
+}
+
+__fenv_static inline int
+feraiseexcept(int __excepts)
+{
+ fexcept_t fcsr;
+
+ __excepts &= FE_ALL_EXCEPT;
+ __cfc1(fcsr);
+ fcsr |= __excepts | (__excepts << _FCSR_CAUSE_SHIFT);
+ __ctc1(fcsr);
+
+ return (0);
+}
+
+__fenv_static inline int
+fetestexcept(int __excepts)
+{
+ fexcept_t fcsr;
+
+ __excepts &= FE_ALL_EXCEPT;
+ __cfc1(fcsr);
+
+ return (fcsr & __excepts);
+}
+
+__fenv_static inline int
+fegetround(void)
+{
+ fexcept_t fcsr;
+
+ __cfc1(fcsr);
+
+ return (fcsr & _ROUND_MASK);
+}
+
+__fenv_static inline int
+fesetround(int __round)
+{
+ fexcept_t fcsr;
+
+ if (__round & ~_ROUND_MASK)
+ return (-1);
+
+ __cfc1(fcsr);
+ fcsr &= ~_ROUND_MASK;
+ fcsr |= __round;
+ __ctc1(fcsr);
+
+ return (0);
+}
+
+__fenv_static inline int
+fegetenv(fenv_t *__envp)
+{
+
+ __cfc1(*__envp);
+
+ return (0);
+}
+
+__fenv_static inline int
+feholdexcept(fenv_t *__envp)
+{
+ fexcept_t fcsr;
+
+ __cfc1(fcsr);
+ *__envp = fcsr;
+ fcsr &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
+ __ctc1(fcsr);
+
+ return (0);
+}
+
+__fenv_static inline int
+fesetenv(const fenv_t *__envp)
+{
+
+ __ctc1(*__envp);
+
+ return (0);
+}
+
+__fenv_static inline int
+feupdateenv(const fenv_t *__envp)
+{
+ fexcept_t fcsr;
+
+ __cfc1(fcsr);
+ fesetenv(__envp);
+ feraiseexcept(fcsr);
+
+ return (0);
+}
+#endif /* !SOFTFLOAT */
+
+#if __BSD_VISIBLE
+
+/* We currently provide no external definitions of the functions below. */
+
+#ifdef SOFTFLOAT
+int feenableexcept(int __mask);
+int fedisableexcept(int __mask);
+int fegetexcept(void);
+#else
+static inline int
+feenableexcept(int __mask)
+{
+ fenv_t __old_fcsr, __new_fcsr;
+
+ __cfc1(__old_fcsr);
+ __new_fcsr = __old_fcsr | (__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT;
+ __ctc1(__new_fcsr);
+
+ return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
+}
+
+static inline int
+fedisableexcept(int __mask)
+{
+ fenv_t __old_fcsr, __new_fcsr;
+
+ __cfc1(__old_fcsr);
+ __new_fcsr = __old_fcsr & ~((__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT);
+ __ctc1(__new_fcsr);
+
+ return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
+}
+
+static inline int
+fegetexcept(void)
+{
+ fexcept_t fcsr;
+
+ __cfc1(fcsr);
+
+ return ((fcsr & _ENABLE_MASK) >> _ENABLE_SHIFT);
+}
+
+#endif /* !SOFTFLOAT */
+
+#endif /* __BSD_VISIBLE */
+
+__END_DECLS
+
+#endif /* !_FENV_H_ */
--- /dev/null
+++ openlibm-0.5.4+dfsg/mips/Make.files
@@ -0,0 +1 @@
+$(CUR_SRCS) = fenv.c
--- /dev/null
+++ openlibm-0.5.4+dfsg/mips/fenv.c
@@ -0,0 +1,67 @@
+/*-
+ * Copyright (c) 2004 David Schultz <d...@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#define __fenv_static
+#include "openlibm_fenv.h"
+
+#ifdef __GNUC_GNU_INLINE__
+#error "This file must be compiled with C99 'inline' semantics"
+#endif
+
+/*
+ * Hopefully the system ID byte is immutable, so it's valid to use
+ * this as a default environment.
+ */
+const fenv_t __fe_dfl_env = 0;
+
+#ifdef SOFTFLOAT
+#define __set_env(env, flags, mask, rnd) env = ((flags) \
+ | (mask)<<_FPUSW_SHIFT \
+ | (rnd) << 24)
+#define __env_flags(env) ((env) & FE_ALL_EXCEPT)
+#define __env_mask(env) (((env) >> _FPUSW_SHIFT) \
+ & FE_ALL_EXCEPT)
+#define __env_round(env) (((env) >> 24) & _ROUND_MASK)
+#include "fenv-softfloat.h"
+#endif
+
+extern inline int feclearexcept(int __excepts);
+extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
+extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
+extern inline int feraiseexcept(int __excepts);
+extern inline int fetestexcept(int __excepts);
+extern inline int fegetround(void);
+extern inline int fesetround(int __round);
+extern inline int fegetenv(fenv_t *__envp);
+extern inline int feholdexcept(fenv_t *__envp);
+extern inline int fesetenv(const fenv_t *__envp);
+extern inline int feupdateenv(const fenv_t *__envp);
+extern inline int feenableexcept(int __mask);
+extern inline int fedisableexcept(int __mask);
+extern inline int fegetexcept(void);
+
--- openlibm-0.5.4+dfsg.orig/src/Make.files
+++ openlibm-0.5.4+dfsg/src/Make.files
@@ -38,6 +38,7 @@ endif
ifneq ($(ARCH), arm)
ifneq ($(ARCH), powerpc)
+ifneq ($(ARCH), mips)
# C99 long double functions
$(CUR_SRCS) += s_copysignl.c s_fabsl.c s_llrintl.c s_lrintl.c s_modfl.c
@@ -58,6 +59,7 @@ $(CUR_SRCS) += e_acosl.c e_asinl.c e_ata
s_clogl.c s_ctanhl.c s_ccosl.c s_cbrtl.c
endif
endif
+endif
# C99 complex functions
$(CUR_SRCS) += s_ccosh.c s_ccoshf.c s_cexp.c s_cexpf.c \
--- openlibm-0.5.4+dfsg.orig/src/fpmath.h
+++ openlibm-0.5.4+dfsg/src/fpmath.h
@@ -39,6 +39,8 @@
#endif
#elif defined(__powerpc__)
#include "powerpc_fpmath.h"
+#elif defined(__mips__)
+#include "mips_fpmath.h"
#endif
/* Definitions provided directly by GCC and Clang. */
--- /dev/null
+++ openlibm-0.5.4+dfsg/src/mips_fpmath.h
@@ -0,0 +1,57 @@
+/*-
+ * Copyright (c) 2002, 2003 David Schultz <d...@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+union IEEEl2bits {
+ long double e;
+ struct {
+#ifndef __MIPSEB__
+ unsigned int manl :32;
+ unsigned int manh :20;
+ unsigned int exp :11;
+ unsigned int sign :1;
+#else
+ unsigned int sign :1;
+ unsigned int exp :11;
+ unsigned int manh :20;
+ unsigned int manl :32;
+#endif
+ } bits;
+};
+
+#define LDBL_NBIT 0
+#define mask_nbit_l(u) ((void)0)
+#define LDBL_IMPLICIT_NBIT
+
+#define LDBL_MANH_SIZE 20
+#define LDBL_MANL_SIZE 32
+
+#define LDBL_TO_ARRAY32(u, a) do { \
+ (a)[0] = (uint32_t)(u).bits.manl; \
+ (a)[1] = (uint32_t)(u).bits.manh; \
+} while(0)
+
