Le 04/12/2019 à 18:51, Laurent Bonnaud a écrit : > On 04/12/2019 16.15, Brice Goglin wrote: > >> PCIe links (since Gen3) are encoded 128 data rate over 130 signal rate. >> That's why you get 3.93 (truncated to 3.9). We decided to keep that >> value exact in hwloc because the data/signal rate is different among >> PCIe generations. We could round it up to 4 in the lstopo output, but I >> am not sure where to start (PCIe Gen4 16x is 31.5GB/s instead of 32 and >> Gen5 will be 63 instead of 64, those are harder to round up). > Thanks for the detailed explanation! > > How about displaying the PCIe generation and number of links?
We often get similar requests for various hardware attributes. Unfortunately, hwloc is not an exhaustive inventory tool. lstopo is the visible part of a library for managing hardware locality. Adding many somehow-unrelated hardware details might be risky (slow down the discovery process, make the API larger, make the ABI harder to maintain, etc). We rather tell people to use dedicated tools for getting hardware-specific details. In the case of PCI Gen + number of lanes, there's a notion of "supported maximal" rate per lane and "current" rate (high-end GPUs slowdown PCI lanes when idle). I'd rather not handle all these details in hwloc. Brice
