A decade ago, Saraswat's research group was the first to begin developing a new 
kind of chip architecture: the 3-dimensional integrated circuit (3-D IC). 
Compared to the 2-D planar chips in computers today, 3-D chips can provide the 
same processing power with a reduced chip surface area. Also, instead of having 
long, twisting highways of wires, the stacked chips in 3-D ICs allow for short 
wires much like elevator shafts, as Professor Chidsey puts it-mitigating the 
problem of delay in the wires. Moreover, 3-D IC architecture allows the 
integration of all kinds of chips, since chips that require different 
technologies or materials can be stacked together.

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It's easy to define and describe a nanometer: a nanometer is a billionth of a meter. That's a millionth of a 
pinhead, a thousandth of a red blood cell diameter, or the length of a line of ten hydrogen atoms rubbing 
shoulders. If only knowing what nanotechnology really means were as simple: "Have you heard the story of 
the elephant and the blind man?" Professor Krishna Saraswat chuckles. "Nanotechnology has different 
meanings to different people, but the conventional definition is the science of material patterned at the 
1-100 nm length scale," notes Professor Michael McGehee. Professor Chris Chidsey muses, 
"Nanotechnology is a concept that is largely designed to capture people's imagination rather than 
describe a particular type of research. It's largely an attempt to portray a unified vision for a pretty 
wide-ranging group of activities that might not otherwise get recognized."
A decade ago, Saraswat's research group was the first to begin developing a new 
kind of chip architecture: the 3-dimensional integrated circuit (3-D IC). 
Compared to the 2-D planar chips in computers today, 3-D chips can provide the 
same processing power with a reduced chip surface area. Also, instead of having 
long, twisting highways of wires, the stacked chips in 3-D ICs allow for short 
wires much like elevator shafts, as Professor Chidsey puts it-mitigating the 
problem of delay in the wires. Moreover, 3-D IC architecture allows the 
integration of all kinds of chips, since chips that require different 
technologies or materials can be stacked together.
The main challenge in 3-D IC design is performance-weakening heat dissipation, 
which is already a problem in 2-D chips, as any Stanford students who have 
written a term paper with their laptops on their laps know. The multi-layer 
design of 3-D ICs exacerbates the problem, and Mechanical Engineering 
Professors Ken Goodson and Tom Kenney have been working on flowing fluid 
through microchannels incorporated in the chips to conduct the heat away.





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