Hi, sorry, output from the phenon processor was using the old version. Attached is the output after patching cpuid.
Cheers, Stefan.
eax in eax ebx ecx edx 00000000 00000005 68747541 444d4163 69746e65 00000001 00100f42 01040800 00802009 178bfbff 00000002 00000000 00000000 00000000 00000000 00000003 00000000 00000000 00000000 00000000 00000004 00000000 00000000 00000000 00000000 00000005 00000040 00000040 00000003 00000000 80000000 8000001b 68747541 444d4163 69746e65 80000001 00100f42 10001857 000037ff efd3fbff 80000002 20444d41 6e656850 74286d6f 4920296d 80000003 34582049 35303920 72502065 7365636f 80000004 00726f73 00000000 00000000 00000000 80000005 ff30ff10 ff30ff20 40020140 40020140 80000006 20800000 42004200 02008140 0030b140 80000007 00000000 00000000 00000000 000001f9 80000008 00003030 00000000 00002003 00000000 80000009 00000000 00000000 00000000 00000000 8000000a 00000001 00000040 00000000 0000000f 8000000b 00000000 00000000 00000000 00000000 8000000c 00000000 00000000 00000000 00000000 8000000d 00000000 00000000 00000000 00000000 8000000e 00000000 00000000 00000000 00000000 8000000f 00000000 00000000 00000000 00000000 80000010 00000000 00000000 00000000 00000000 80000011 00000000 00000000 00000000 00000000 80000012 00000000 00000000 00000000 00000000 80000013 00000000 00000000 00000000 00000000 80000014 00000000 00000000 00000000 00000000 80000015 00000000 00000000 00000000 00000000 80000016 00000000 00000000 00000000 00000000 80000017 00000000 00000000 00000000 00000000 80000018 00000000 00000000 00000000 00000000 80000019 f0300000 60100000 00000000 00000000 8000001a 00000003 00000000 00000000 00000000 8000001b 0000001f 00000000 00000000 00000000 Vendor ID: "AuthenticAMD"; CPUID level 5 AMD-specific functions Version 00100f42: Family: 15 Model: 4 [] Standard feature flags 178bfbff: Floating Point Unit Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter (with RDTSC and CR4 disable bit) Model Specific Registers with RDMSR & WRMSR PAE - Page Address Extensions Machine Check Exception COMPXCHG8B Instruction APIC SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions MTRR - Memory Type Range Registers Global paging extension Machine Check Architecture Conditional Move Instruction PAT - Page Attribute Table PSE-36 - Page Size Extensions CLFLUSH instruction MMX instructions FXSAVE/FXRSTOR SSE Extensions SSE2 Extensions HTT: hyperthreading technology Generation: 15 Model: 4 Extended feature flags efd3fbff: Floating Point Unit Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter (with RDTSC and CR4 disable bit) Model Specific Registers with RDMSR & WRMSR PAE - Page Address Extensions Machine Check Exception COMPXCHG8B Instruction APIC SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions MTRR - Memory Type Range Registers Global paging extension Machine Check Architecture Conditional Move Instruction PAT - Page Attribute Table PSE-36 - Page Size Extensions NX - No execute page protection MMXext - AMD extensions to MMX instructions MMX instructions FXSAVE/FXRSTOR FFXSR: FXSAVE/FXRSTOR instruction optimizations 1 GB large page support RDTSCP LM: Long mode 3DNow! Instruction Extensions 3DNOW! instructions LahfSahf - LAHF and SAHF instructions in 64 bit mode CmpLegacy - core multiprocessing legacy mode SVM - secure virtual machine ExtApic - extended APIC space AltMovCR8 - LOCK MOV CR0 means MOV CR8 ABM - advanced bit manipulation: LZCNT instruction SSE4A - EXTRQ INSERTQ MOVNTSS MOVNTSD MisAlignSse - misaligned sse mode 3DNowPrefetch - PREFETCH PREFETCHW OSVW - OS visible workaround IBS - Instruction based sampling SKINIT - SKINIT STGI WDT - Watchdog timer support Processor name string: AMD Phenom(tm) II X4 905e Processor L1 Cache Information: 2/4-MB Pages: Data TLB: associativity 255-way #entries 48 Instruction TLB: associativity 255-way #entries 16 4-KB Pages: Data TLB: associativity 255-way #entries 48 Instruction TLB: associativity 255-way #entries 32 L1 Data cache: size 64 KB associativity 2-way lines per tag 1 line size 64 L1 Instruction cache: size 64 KB associativity 2-way lines per tag 1 line size 64 L2 Cache Information: 2/4-MB Pages: Data TLB: associativity L2 off #entries 128 Instruction TLB: associativity L2 off #entries 0 4-KB Pages: Data TLB: associativity 2-way #entries 0 Instruction TLB: associativity 2-way #entries 0 size 2 KB associativity L2 off lines per tag 129 line size 64 Advanced Power Management Feature Flags Has temperature sensing diode Maximum linear address: 48; maximum phys address 48 SVM revision: 1 NASID: Number of Address space identifiers 64 NP: Nested paging LbrVirt: LBR Virtualisation SVM Lock NRIPS: NRIP Save
