Author: aurel32
Date: 2014-10-27 21:39:20 +0000 (Mon, 27 Oct 2014)
New Revision: 6317
Added:
glibc-package/trunk/debian/patches/amd64/cvs-slow-sse42.diff
Modified:
glibc-package/trunk/debian/changelog
glibc-package/trunk/debian/patches/series
Log:
patches/amd64/cvs-slow-sse42.diff: backport patch from upstream to fix
a performance issue with strcmp and friends functions on some machines.
Modified: glibc-package/trunk/debian/changelog
===================================================================
--- glibc-package/trunk/debian/changelog 2014-10-27 21:34:59 UTC (rev
6316)
+++ glibc-package/trunk/debian/changelog 2014-10-27 21:39:20 UTC (rev
6317)
@@ -5,6 +5,8 @@
Workarounds a kfreebsd 9.0 to 10.1 ABI break. Closes: #740509.
* patches/hppa/cvs-sigrtmin.diff: backport patch from upstream to change
__SIGRTMIN to match other architectures. Closes: #766605.
+ * patches/amd64/cvs-slow-sse42.diff: backport patch from upstream to fix
+ a performance issue with strcmp and friends functions on some machines.
-- Aurelien Jarno <[email protected]> Mon, 27 Oct 2014 21:36:32 +0100
Added: glibc-package/trunk/debian/patches/amd64/cvs-slow-sse42.diff
===================================================================
--- glibc-package/trunk/debian/patches/amd64/cvs-slow-sse42.diff
(rev 0)
+++ glibc-package/trunk/debian/patches/amd64/cvs-slow-sse42.diff
2014-10-27 21:39:20 UTC (rev 6317)
@@ -0,0 +1,103 @@
+2014-10-27 Andreas Schwab <[email protected]>
+
+ [BZ #17501]
+ * sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Fix
+ check for Slow_SSE4_2 feature bit.
+ * sysdeps/i386/i686/multiarch/strcmp.S (STRCMP): Likewise.
+ * sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
+ * sysdeps/x86_64/multiarch/strcmp.S (STRCMP, __strcascmp):
+ Likewise. Fix check for Fast_Unaligned_Load feature bit.
+
+--- a/sysdeps/i386/i686/multiarch/strcasecmp.S
++++ b/sysdeps/i386/i686/multiarch/strcasecmp.S
+@@ -37,7 +37,7 @@ ENTRY(__strcasecmp)
+ leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax
+ testl $bit_SSE4_2,
CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ jz 2f
+- testl $bit_Slow_SSE4_2,
CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
++ testl $bit_Slow_SSE4_2,
FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ jnz 2f
+ leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax
+ 2: popl %ebx
+@@ -58,7 +58,7 @@ ENTRY(__strcasecmp)
+ leal __strcasecmp_ssse3, %eax
+ testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
+ jz 2f
+- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
++ testl $bit_Slow_SSE4_2,
FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
+ jnz 2f
+ leal __strcasecmp_sse4_2, %eax
+ 2: ret
+--- a/sysdeps/i386/i686/multiarch/strcmp.S
++++ b/sysdeps/i386/i686/multiarch/strcmp.S
+@@ -68,7 +68,7 @@ ENTRY(STRCMP)
+ leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax
+ testl $bit_SSE4_2,
CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ jz 2f
+- testl $bit_Slow_SSE4_2,
CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
++ testl $bit_Slow_SSE4_2,
FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ jnz 2f
+ leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax
+ 2: popl %ebx
+@@ -89,7 +89,7 @@ ENTRY(STRCMP)
+ leal __STRCMP_SSSE3, %eax
+ testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
+ jz 2f
+- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
++ testl $bit_Slow_SSE4_2,
FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
+ jnz 2f
+ leal __STRCMP_SSE4_2, %eax
+ 2: ret
+--- a/sysdeps/i386/i686/multiarch/strncase.S
++++ b/sysdeps/i386/i686/multiarch/strncase.S
+@@ -37,7 +37,7 @@ ENTRY(__strncasecmp)
+ leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax
+ testl $bit_SSE4_2,
CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ jz 2f
+- testl $bit_Slow_SSE4_2,
CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
++ testl $bit_Slow_SSE4_2,
FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ jnz 2f
+ leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax
+ 2: popl %ebx
+@@ -58,7 +58,7 @@ ENTRY(__strncasecmp)
+ leal __strncasecmp_ssse3, %eax
+ testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
+ jz 2f
+- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
++ testl $bit_Slow_SSE4_2,
FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
+ jnz 2f
+ leal __strncasecmp_sse4_2, %eax
+ 2: ret
+--- a/sysdeps/x86_64/multiarch/strcmp.S
++++ b/sysdeps/x86_64/multiarch/strcmp.S
+@@ -91,10 +91,10 @@ ENTRY(STRCMP)
+ 1:
+ #ifdef USE_AS_STRCMP
+ leaq __strcmp_sse2_unaligned(%rip), %rax
+- testl $bit_Fast_Unaligned_Load,
__cpu_features+CPUID_OFFSET+index_Fast_Unaligned_Load(%rip)
++ testl $bit_Fast_Unaligned_Load,
__cpu_features+FEATURE_OFFSET+index_Fast_Unaligned_Load(%rip)
+ jnz 3f
+ #else
+- testl $bit_Slow_SSE4_2,
__cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
++ testl $bit_Slow_SSE4_2,
__cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
+ jnz 2f
+ leaq STRCMP_SSE42(%rip), %rax
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
+@@ -120,7 +120,7 @@ ENTRY(__strcasecmp)
+ testl $bit_AVX_Usable,
__cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
+ jnz 3f
+ # endif
+- testl $bit_Slow_SSE4_2,
__cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
++ testl $bit_Slow_SSE4_2,
__cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
+ jnz 2f
+ leaq __strcasecmp_sse42(%rip), %rax
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
+@@ -146,7 +146,7 @@ ENTRY(__strncasecmp)
+ testl $bit_AVX_Usable,
__cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
+ jnz 3f
+ # endif
+- testl $bit_Slow_SSE4_2,
__cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
++ testl $bit_Slow_SSE4_2,
__cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
+ jnz 2f
+ leaq __strncasecmp_sse42(%rip), %rax
+ testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
Modified: glibc-package/trunk/debian/patches/series
===================================================================
--- glibc-package/trunk/debian/patches/series 2014-10-27 21:34:59 UTC (rev
6316)
+++ glibc-package/trunk/debian/patches/series 2014-10-27 21:39:20 UTC (rev
6317)
@@ -51,6 +51,7 @@
amd64/submitted-rwlock-stack-imbalance.diff
amd64/local-blacklist-on-TSX-Haswell.diff
+amd64/cvs-slow-sse42.diff
arm/local-ioperm.diff
arm/local-lowlevellock.diff
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