> Not using them in one insn is insufficient anyway. In what I think ought > to be true in theory, if fr5L is the target of a fp op, you must wait > at least FPU pipe length clock cycles before using fr5R or fr5L. In > practice,
There is already a scheduling model present in GCC. If you have a testcase showing a problem, please submit a PR. What needs to be looked at is enhancing this model to account for the extra stall that may be present in this situation. However, we may not have the information needed to model this. Jeff Law who did the scheduling model had an NDA agreement that allowed access to information about instruction timing. Dave -- J. David Anglin [EMAIL PROTECTED] National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
