diff -ur linux-3.2.23-old/arch/ia64/pci/fixup.c linux-3.2.23/arch/ia64/pci/fixup.c
--- linux-3.2.23-old/arch/ia64/pci/fixup.c	2012-09-15 10:53:02.000000000 +0200
+++ linux-3.2.23/arch/ia64/pci/fixup.c	2012-09-15 10:59:43.000000000 +0200
@@ -67,3 +67,42 @@
 	}
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
+
+
+/*
+ * Fixup the EFI-BIOS bug of Intel's SR870 platform
+ *
+ * The EFI-BIOS of Intel's SR870BH2 and SR870BN4 including their OEM
+ * equivalents by Fujitsu and Dell doesn't configure the built-in ICH4-L IDE
+ * hostadapter correctly. The 6th resource of the ICH4-L is a memory resource;
+ * Intel's datasheet "Intel 82801DB I/O Controller Hub 4 (ICH4)" (Document
+ * Number: 290744-001) states in section "10.1.15 EXBAR - Expansion Base
+ * Address Register (IDE-D31:F1)" on page 389:
+ * "This is a memory mapped BAR that requires 1 KB of DWord-aligned memory
+ * that is Intel reserved for future functionality. BIOS needs to program the
+ * base address for a 1-KB memory space."
+ * The EFI-BIOS doesn't care about that and doesn't configure the memory
+ * resource. Since the PCI configuration registers have their default values
+ * after reset, the memory resource is configured with 0x0-0x3FF. The Kernel
+ * can't use it due to memory address conflicts, and the ata_piix driver fails
+ * to initialize.
+ * 
+ * This quirk function disables the EXBAR memory resource of the device if it
+ * has the default values after reset.
+ */
+
+static void __devinit pci_fixup_sr870_ich4l(struct pci_dev *pdev)
+{
+    struct resource *r;
+
+    r = &pdev->resource[5];
+    if ((r->flags & IORESOURCE_MEM)
+        && r->start == 0 && r->end != 0) {
+            dev_info(&pdev->dev,
+                "SR870 EFI-BIOS bug workaround; fake an unimplemented EXBAR "
+                "resource, which is Intel reserved for future functionality.\n");
+            r->flags = 0;
+            r->end = 0;
+    }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11, pci_fixup_sr870_ich4l);