On Wed, Dec 30, 2020 at 12:38:53AM +0100, Karsten Hilbert wrote: > I agree. It seems quite likely to be more setup of the device.
To be precise I do not know how to issue two back to back 'S' without a 'C' occurring in between. 1.007.001 S Ii 0002 1.007.000 S Ci 0342 c0 83 0008 0000 0342 That's the only difference left between the two traces. Does it look like multithreading is required for it - i.e. issue 'S Ii' with a timeout and in parallel (but after 'S Ii' is issued) do rest of the things and then sync with 'C Ii'? On the face of it, it's weird if multithreading is required for a serial communication where there is one link and two devices at both ends of it. But may be the device is designed to not respond to Ii until it sees those Cis (or timeout). Will try anyway.
