> > 3. How are DMA buffers used outside the kernel? Do user programs get a > > pointer to the DMA buffer (in theory) from the device driver or is the data > > copied to another buffer allocated by an user program? > > > There are already non-coherent cache PPC archs (8xx, 4xx) just look > how all this implemented there, don't reinvent the wheel.
Unfortunately, he has to do things a bit differently. He can't afford to have the kernel BAT mapping cover his non-cacheable pages. Thus he needs a reserved pool. Last I looked at our coherent code, it didn't reserve memory at all, just address space, thus assuming the CPU can handle having both a caheable and a non-cacheable mapping of the same pages... (On 6xx this is deadly even if you don't access those cacheable pages because the CPU prefetch may do it for you). Ben. -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
