Source: qt4-x11 Severity: important Tags: patch Hello,
This patch is needed to make qt4-x11 buildable on armhf, right now the package fails due to thumb2 errors ([1]). The patches have been backported from Ubuntu. Please consider integrating this patch. Konstantinos [1]: http://buildd.debian-ports.org/fetch.php?pkg=qt4-x11&arch=armhf&ver=4%3A4.7.2-1&stamp=1299739506&file=log&as=raw -- System Information: Debian Release: squeeze/sid Architecture: armhf (armv7l) Kernel: Linux 2.6.31.14-efikamx (PREEMPT) Locale: LANG=en_US.UTF-8, LC_CTYPE=en_US.UTF-8 (charmap=UTF-8) Shell: /bin/sh linked to /bin/dash
diff -ruN qt4-x11-4.7.2/debian/changelog qt4-x11-4.7.2.armhf//debian/changelog --- qt4-x11-4.7.2/debian/changelog 2011-03-07 12:42:22.000000000 +0200 +++ qt4-x11-4.7.2.armhf//debian/changelog 2011-03-15 03:55:02.000000000 +0200 @@ -1,3 +1,11 @@ +qt4-x11 (4:4.7.2-1.1) unstable; urgency=low + + * armhf support + backport from Ubuntu: + * http://launchpadlibrarian.net/66374974/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch + + -- Konstantinos Margaritis <mar...@debian.org> Mon, 14 Mar 2011 20:02:08 +0000 + qt4-x11 (4:4.7.2-1) unstable; urgency=low * New upstream release. diff -ruN qt4-x11-4.7.2/debian/patches/94_armv6_uname_entry.diff qt4-x11-4.7.2.armhf//debian/patches/94_armv6_uname_entry.diff --- qt4-x11-4.7.2/debian/patches/94_armv6_uname_entry.diff 1970-01-01 02:00:00.000000000 +0200 +++ qt4-x11-4.7.2.armhf//debian/patches/94_armv6_uname_entry.diff 2011-03-13 02:34:35.000000000 +0200 @@ -0,0 +1,15 @@ +Description: Add armv6 uname entry for armhf +--- + +--- a/configure 2011-03-10 15:25:58.000000000 +0200 ++++ b/configure 2011-03-11 10:40:13.837312856 +0200 +@@ -182,6 +182,9 @@ + armel) + UNAME_MACHINE="armv5tel" + ;; ++ armhf) ++ UNAME_MACHINE="armv6" ++ ;; + hppa) + UNAME_MACHINE="parisc64" + ;; diff -ruN qt4-x11-4.7.2/debian/patches/95_neon_flags.patch qt4-x11-4.7.2.armhf//debian/patches/95_neon_flags.patch --- qt4-x11-4.7.2/debian/patches/95_neon_flags.patch 1970-01-01 02:00:00.000000000 +0200 +++ qt4-x11-4.7.2.armhf//debian/patches/95_neon_flags.patch 2011-03-13 02:34:01.000000000 +0200 @@ -0,0 +1,18 @@ +## Description: add some description +## Origin/Author: add some origin or author +## Bug: bug URL +Index: qt4-x11-4.7.2/src/gui/gui.pro +=================================================================== +--- qt4-x11-4.7.2.orig/src/gui/gui.pro 2011-03-06 21:41:47.058276259 +0200 ++++ qt4-x11-4.7.2/src/gui/gui.pro 2011-03-06 21:38:16.569232507 +0200 +@@ -65,9 +65,9 @@ + neon:*-g++* { + DEFINES += QT_HAVE_NEON + HEADERS += $$NEON_HEADERS +- SOURCES += $$NEON_SOURCES + + DRAWHELPER_NEON_ASM_FILES = $$NEON_ASM ++ DRAWHELPER_NEON_ASM_FILES += $$NEON_SOURCES + + neon_compiler.commands = $$QMAKE_CXX -c -mfpu=neon + neon_compiler.commands += $(CXXFLAGS) $(INCPATH) ${QMAKE_FILE_IN} -o ${QMAKE_FILE_OUT} diff -ruN qt4-x11-4.7.2/debian/patches/series qt4-x11-4.7.2.armhf//debian/patches/series --- qt4-x11-4.7.2/debian/patches/series 2011-03-07 12:42:08.000000000 +0200 +++ qt4-x11-4.7.2.armhf//debian/patches/series 2011-03-15 04:09:27.000000000 +0200 @@ -31,5 +31,9 @@ 89_powerpc_opts.diff 91_s390_use_gstabs.diff 92_armel_gcc43_valist_compat.diff +x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch +94_armv6_uname_entry.diff +95_neon_flags.patch 96_webkit_no_gc_sections.diff 99_hppa_bug561203_decrease_failure_rate.diff +debian-changes-4:4.7.2-1.1 diff -ruN qt4-x11-4.7.2/debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch qt4-x11-4.7.2.armhf//debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch --- qt4-x11-4.7.2/debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch 1970-01-01 02:00:00.000000000 +0200 +++ qt4-x11-4.7.2.armhf//debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch 2011-03-15 00:43:15.000000000 +0200 @@ -0,0 +1,200 @@ +From 7aaf387cdb578327017169a9c97bcf6c0581a780 Mon Sep 17 00:00:00 2001 +From: michaedw in build chroot <bu...@ctbu-bld5.cisco.com> +Date: Mon, 14 Mar 2011 01:52:46 +0000 +Subject: [PATCH] Use GCC intrinsics for armv6 atomic operations + +--- + src/corelib/arch/qatomic_armv6.h | 146 +++++++------------------------------ + 1 files changed, 28 insertions(+), 118 deletions(-) + +diff --git a/src/corelib/arch/qatomic_armv6.h b/src/corelib/arch/qatomic_armv6.h +index 53f7907..7dfc002 100644 +--- a/src/corelib/arch/qatomic_armv6.h ++++ b/src/corelib/arch/qatomic_armv6.h +@@ -104,155 +104,65 @@ Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isFetchAndAddWaitFree() + + inline bool QBasicAtomicInt::ref() + { +- register int newValue; +- register int result; +- asm volatile("0:\n" +- "ldrex %[newValue], [%[_q_value]]\n" +- "add %[newValue], %[newValue], #1\n" +- "strex %[result], %[newValue], [%[_q_value]]\n" +- "teq %[result], #0\n" +- "bne 0b\n" +- : [newValue] "=&r" (newValue), +- [result] "=&r" (result), +- "+m" (_q_value) +- : [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return newValue != 0; ++ return __sync_add_and_fetch(&_q_value, 1) != 0; + } + + inline bool QBasicAtomicInt::deref() + { +- register int newValue; +- register int result; +- asm volatile("0:\n" +- "ldrex %[newValue], [%[_q_value]]\n" +- "sub %[newValue], %[newValue], #1\n" +- "strex %[result], %[newValue], [%[_q_value]]\n" +- "teq %[result], #0\n" +- "bne 0b\n" +- : [newValue] "=&r" (newValue), +- [result] "=&r" (result), +- "+m" (_q_value) +- : [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return newValue != 0; ++ return __sync_sub_and_fetch(&_q_value, 1) != 0; + } + + inline bool QBasicAtomicInt::testAndSetOrdered(int expectedValue, int newValue) + { +- register int result; +- asm volatile("0:\n" +- "ldrex %[result], [%[_q_value]]\n" +- "eors %[result], %[result], %[expectedValue]\n" +- "strexeq %[result], %[newValue], [%[_q_value]]\n" +- "teqeq %[result], #1\n" +- "beq 0b\n" +- : [result] "=&r" (result), +- "+m" (_q_value) +- : [expectedValue] "r" (expectedValue), +- [newValue] "r" (newValue), +- [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return result == 0; ++ return __sync_bool_compare_and_swap(&_q_value, expectedValue, newValue); + } + + inline int QBasicAtomicInt::fetchAndStoreOrdered(int newValue) + { +- register int originalValue; +- register int result; +- asm volatile("0:\n" +- "ldrex %[originalValue], [%[_q_value]]\n" +- "strex %[result], %[newValue], [%[_q_value]]\n" +- "teq %[result], #0\n" +- "bne 0b\n" +- : [originalValue] "=&r" (originalValue), +- [result] "=&r" (result), +- "+m" (_q_value) +- : [newValue] "r" (newValue), +- [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return originalValue; ++ if (!newValue) ++ return __sync_fetch_and_and(&_q_value, 0); ++ else ++ { ++ int expectedValue = 0; ++ int oldValue; ++ do { ++ oldValue = __sync_val_compare_and_swap(&_q_value, expectedValue, newValue); ++ } while (oldValue != expectedValue); ++ return oldValue; ++ } + } + + inline int QBasicAtomicInt::fetchAndAddOrdered(int valueToAdd) + { +- register int originalValue; +- register int newValue; +- register int result; +- asm volatile("0:\n" +- "ldrex %[originalValue], [%[_q_value]]\n" +- "add %[newValue], %[originalValue], %[valueToAdd]\n" +- "strex %[result], %[newValue], [%[_q_value]]\n" +- "teq %[result], #0\n" +- "bne 0b\n" +- : [originalValue] "=&r" (originalValue), +- [newValue] "=&r" (newValue), +- [result] "=&r" (result), +- "+m" (_q_value) +- : [valueToAdd] "r" (valueToAdd), +- [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return originalValue; ++ return __sync_fetch_and_add(&_q_value, valueToAdd); + } + + template <typename T> + Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetOrdered(T *expectedValue, T *newValue) + { +- register T *result; +- asm volatile("0:\n" +- "ldrex %[result], [%[_q_value]]\n" +- "eors %[result], %[result], %[expectedValue]\n" +- "strexeq %[result], %[newValue], [%[_q_value]]\n" +- "teqeq %[result], #1\n" +- "beq 0b\n" +- : [result] "=&r" (result), +- "+m" (_q_value) +- : [expectedValue] "r" (expectedValue), +- [newValue] "r" (newValue), +- [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return result == 0; ++ return __sync_bool_compare_and_swap(&_q_value, expectedValue, newValue); + } + + template <typename T> + Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndStoreOrdered(T *newValue) + { +- register T *originalValue; +- register int result; +- asm volatile("0:\n" +- "ldrex %[originalValue], [%[_q_value]]\n" +- "strex %[result], %[newValue], [%[_q_value]]\n" +- "teq %[result], #0\n" +- "bne 0b\n" +- : [originalValue] "=&r" (originalValue), +- [result] "=&r" (result), +- "+m" (_q_value) +- : [newValue] "r" (newValue), +- [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return originalValue; ++ if (!newValue) ++ return __sync_fetch_and_and(&_q_value, 0); ++ else ++ { ++ T* expectedValue = 0; ++ T* oldValue; ++ do { ++ oldValue = __sync_val_compare_and_swap(&_q_value, expectedValue, newValue); ++ } while (oldValue != expectedValue); ++ return oldValue; ++ } + } + + template <typename T> + Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndAddOrdered(qptrdiff valueToAdd) + { +- register T *originalValue; +- register T *newValue; +- register int result; +- asm volatile("0:\n" +- "ldrex %[originalValue], [%[_q_value]]\n" +- "add %[newValue], %[originalValue], %[valueToAdd]\n" +- "strex %[result], %[newValue], [%[_q_value]]\n" +- "teq %[result], #0\n" +- "bne 0b\n" +- : [originalValue] "=&r" (originalValue), +- [newValue] "=&r" (newValue), +- [result] "=&r" (result), +- "+m" (_q_value) +- : [valueToAdd] "r" (valueToAdd * sizeof(T)), +- [_q_value] "r" (&_q_value) +- : "cc", "memory"); +- return originalValue; ++ return (T*) __sync_fetch_and_add((volatile int*) &_q_value, valueToAdd); + } + + #else +-- +1.7.0.4 + diff -ruN qt4-x11-4.7.2/debian/rules qt4-x11-4.7.2.armhf//debian/rules --- qt4-x11-4.7.2/debian/rules 2011-03-07 12:42:08.000000000 +0200 +++ qt4-x11-4.7.2.armhf//debian/rules 2011-03-13 02:34:35.000000000 +0200 @@ -35,6 +35,10 @@ extra_configure_opts += -DQT_QLOCALE_USES_FCVT endif +ifeq ($(DEB_HOST_ARCH),armhf) + extra_configure_opts += -arch armv6 +endif + ifeq ($(DEB_HOST_ARCH_OS),linux) ifeq ($(DEB_HOST_ARCH),amd64) platform_arg = linux-g++-64