Package: release.debian.org
Control: affects -1 + src:intel-microcode
X-Debbugs-Cc: [email protected]
User: [email protected]
Usertags: pu
Tags: trixie
Severity: normal
[ Reason ]
I would like to bring the microcode update level for Intel processors in
Bookworm and Trixie to match what we have in Sid and Forky.
This is a microcode security update. A stable upload was suggested by the
Debian security team, since the upload to unstable was close enough to the
next point release that it made sense to do it that way instead of through
a security upload.
This update fixes:
- unspecified functional issues on several processors
- critical functional issues on at least one processor
(Cure Ultra Meteor Lake C0)
- Several security issues (11 CVEs), from information disclosure to
denial of service and system integrity violations (including SMM
and SGX).
[ Impact ]
If this update is not approved, owners of most recent "client" Intel
processors and a few server processors will depend on UEFI updates to be
protected from the issues listed above.
Users of Core Ultra Meteor Lake C0 on some platforms (I understand the
stability issues do not show up on every platform out there) will benefit
from better system stability, since this update fixes a critical
functional issue on the latest widely-deployed *firmware* microcode
update.
[ Tests ]
There were no bug reports from users of Debian Sid or Forky, these
packages have been tested there since 2026-11-04 (sid), 2026-11-06
(forky).
There are no relevant issues reported on this microcode update. It has
been widely exposed upstream (other distributions since 2026-08-12 for
most processors, and Core Ultra Meteor Lake C0 since 2026-09-25) with no
regression reports either upstream, or on the other major distros.
[ Risks ]
Unknown, but not believed to be any different from other Intel microcode
updates.
[ Checklist ]
[x] *all* changes are documented in the d/changelog
[x] I reviewed all changes and I approve them
[x] attach debdiff against the package in (old)stable
[x] the issue is verified as fixed in unstable
[ Changes ]
As per the debdiff, only documentation changes, package documentation
changes, and the binary blob change from upstream.
[ Other info ]
The package version with "~" is needed to guarantee smooth updates to
the next debian release.
--
Henrique de Moraes Holschuh <[email protected]>diff --git a/README.md b/README.md
index 7611474..956d837 100644
--- a/README.md
+++ b/README.md
@@ -1,106 +1,106 @@
-# Intel Processor Microcode Package for Linux
-
-## About
-
-The Intel Processor Microcode Update (MCU) Package provides a mechanism to release updates for security advisories and functional issues, including errata. In addition, MCUs are responsible for starting the SGX enclave (on processors that support the SGX feature), implementing complex behaviors (such as assists), and more. The preferred method to apply MCUs is using the system BIOS. For a subset of Intel's processors, the MCU can also be updated at runtime using the operating system. The Intel Microcode Package shared here contains updates for those processors that support OS loading of MCUs.
-
-## Why update the microcode?
-Updating your microcode can help to mitigate certain potential security vulnerabilities in CPUs as well as address certain functional issues that could, for example, result in unpredictable system behavior such as hangs, crashes, unexpected reboots, data errors, etc. To learn more about applying MCUs to an Intel processor, see [Microcode Update Guidance](https://software.intel.com/security-software-guidance/insights/microcode-update-guidance).
-
-## Loading microcode updates
-
-This package is provided for Linux distributors for inclusion in their OS releases. Intel recommends obtaining the latest MCUs using the OS vendor update mechanism. A good starting point is [OS and Software Vendor](https://software.intel.com/security-software-guidance/insights/guidance-system-administrators-mitigate-transient-execution-side-channel-issues). Expert users can update their microcode directly outside the OS vendor mechanism. However, this method is complex and could result in errors if performed incorrectly. Such errors could include but are not limited to system freezes, inability to boot, performance impacts, logical processors loading different updates, and some updates not taking effect. As a result, this method should be attempted by expert users only.
-
-MCUs are best loaded from the BIOS. Certain MCUs must only be applied from the BIOS. Such MCUs are never packaged in this package since they are not appropriate for OS distribution. An OEM may receive microcode update packages that are a superset of what is contained in this package for inclusion in a BIOS.
-
-OS vendors may choose to provide an MCU that the kernel can consume for early loading. For example, Linux can apply an MCU very early in the kernel boot sequence. In situations where a BIOS update isn't available, early loading is the next best alternative to updating processor microcode. **Microcode states are reset on a power reset, hence its required that the MCU be loaded every time during boot process.**
-
-## Recommendation
-
-Using the initrd method to load an MCU is recommended as this method will load the MCU at the earliest time for the most coverage. Systems that cannot tolerate downtime may use the late-load method to update a running system without a reboot.
-
-## About Processor Signature, Family, Model, Stepping and Platform ID
-
-The Processor Signature is a number identifying the model and version of an Intel processor. It can be obtained using the *CPUID instruction*, via the command *lscpu*, or from the content of */proc/cpuinfo*. It's usually presented as 3 fields: Family, Model, and Stepping.
-
-For example, if a processor returns a value of "0x000906eb" from the *CPUID instruction*:
-
-| Reserved | Extended Family | Extended Model | Reserved | Processor Type | Family Code | Model Number | Stepping ID |
-|:---------|:----------------|:---------------|:---------|:---------------|:------------|:-------------|:------------|
-| 31:28 | 27:20 | 19:16 | 15:14 | 13:12 | 11:8 | 7:4 | 3:0 |
-| xxxx | 00000000b | 1001b | xx | 00b | 0110b | 1110b | 1011b |
-
-
-The corresponding Linux formatted file name will be "06-9e-0b", where:
-- Extended Family + Family = 0x06
-- Extended Model + Model Number = 0x9e
-- Stepping ID = 0xb
-
-A processor may be implemented for multiple platform types. Intel processors have a 3bit Platform ID field in MSR(17H) that specifies the platform type for up to 8 types. An MCU file for a specified processor model may support multiple platforms. The Platform ID(s) supported by an MCU is an 8bit mask where each set bit indicates a platform type that the MCU supports. The Platform ID of a processor can be read in Linux using rdmsr from [msr-tools](https://github.com/intel/msr-tools).
-
-## Microcode update instructions
-
-The [intel-ucode](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode) directory contains binary MCU files named in the `family-model-stepping` format. This file format is supported by most modern Linux distributions. It's generally located in the /lib/firmware directory and can be updated through the microcode reload interface following the late-load update instructions below.
-
-### Early-load update
-To update early loading initrd, consult your Linux distribution on how to package MCU files for early loading. Some distributions use `update-initramfs` or `dracut`. Use the OS vendors recommended method to help ensure that the MCU file is updated for early loading before attempting the late-load procedure below.
-
-### Late-load update
-To update the intel-ucode package to the system:
-1. Ensure the existence of `/sys/devices/system/cpu/microcode/reload`
-2. Download the latest microcode firmware</br> `$ git clone https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.git` or</br> `$ wget https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/main.zip`
-3. Copy `intel-ucode` directory to `/lib/firmware`, overwriting the files in /lib/firmware/intel-ucode/
-4. Write the reload interface to 1 to reload the microcode files, e.g.</br>
- `$ echo 1 > /sys/devices/system/cpu/microcode/reload`</br>
- Microcode updates will be applied automatically without rebooting the system.
-5. Update an existing initramfs so that next time it gets loaded via kernel:</br>
-`$ sudo update-initramfs -u`</br>
-`$ sudo reboot`
-6. Verify that the microcode was updated on boot or reloaded by echo command:</br>
-`$ dmesg | grep microcode` or</br>
-`$ cat /proc/cpuinfo | grep microcode | sort | uniq`
-
-If you are using the OS vendor method to apply an MCU, the above steps may have been done automatically during the update process.
-
-The [intel-ucode-with-caveats](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode-with-caveats) directory contains MCUs that need special handling. The BDX-ML MCU is provided in this directory because it requires special commits in the Linux kernel otherwise updating it might result in unexpected system behavior. OS vendors must ensure that the late loader patches (provided in [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches)) are included in the distribution before packaging the BDX-ML MCU for late-loading.
-
-The [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches) directory consists of kernel patches that address various issues related to applying MCUs.
-
-## Notes
-
-* You can only update to a higher MCU version (downgrade is not possible with the provided instructions)
-* To calculate Family-Model-Stepping, use Linux command:</br>
-`$ printf "%x\n" <number_to_convert_to_hex>`
-* There are multiple ways to check the MCU version number BEFORE update. After cloning this Intel Microcode update repo , run the following:
- - `$ iucode_tool -l intel-ucode | grep -wF sig` ([iucode_tool](https://gitlab.com/iucode-tool/iucode-tool/-/wikis/home) package is required)
- - `$ od -t x4 <Family-Model-Stepping>` will read the first 16 bytes of the microcode binary header specified in \<Family\-Model\-Stepping\>. The third block is the microcode version. For example:
-`$ od -t x4 06-55-04`</br>
-`0000000 00000001 *02000065* 09052019 00050654`
-
-## License
-
-See the [license](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/license) file for details.
-
-## Security Policy
-
-See the [security.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/security.md) file for details.
-
-## Release Note
-
-See the [releasenote.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) file for details.
-
-## Disclaimers
-
-Intel technologiesâ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at [www.intel.com](https://www.intel.com).
-
-No product or component can be absolutely secure.
-
-All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.
-
-The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request.
-
-Intel provides these materials as-is, with no express or implied warranties.
-
-© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
-
+# Intel Processor Microcode Package for Linux
+
+## About
+
+The Intel Processor Microcode Update (MCU) Package provides a mechanism to release updates for security advisories and functional issues, including errata. In addition, MCUs are responsible for starting the SGX enclave (on processors that support the SGX feature), implementing complex behaviors (such as assists), and more. The preferred method to apply MCUs is using the system BIOS. For a subset of Intel's processors, the MCU can also be updated at runtime using the operating system. The Intel Microcode Package shared here contains updates for those processors that support OS loading of MCUs.
+
+## Why update the microcode?
+Updating your microcode can help to mitigate certain potential security vulnerabilities in CPUs as well as address certain functional issues that could, for example, result in unpredictable system behavior such as hangs, crashes, unexpected reboots, data errors, etc. To learn more about applying MCUs to an Intel processor, see [Microcode Update Guidance](https://software.intel.com/security-software-guidance/insights/microcode-update-guidance).
+
+## Loading microcode updates
+
+This package is provided for Linux distributors for inclusion in their OS releases. Intel recommends obtaining the latest MCUs using the OS vendor update mechanism. A good starting point is [OS and Software Vendor](https://software.intel.com/security-software-guidance/insights/guidance-system-administrators-mitigate-transient-execution-side-channel-issues). Expert users can update their microcode directly outside the OS vendor mechanism. However, this method is complex and could result in errors if performed incorrectly. Such errors could include but are not limited to system freezes, inability to boot, performance impacts, logical processors loading different updates, and some updates not taking effect. As a result, this method should be attempted by expert users only.
+
+MCUs are best loaded from the BIOS. Certain MCUs must only be applied from the BIOS. Such MCUs are never packaged in this package since they are not appropriate for OS distribution. An OEM may receive microcode update packages that are a superset of what is contained in this package for inclusion in a BIOS.
+
+OS vendors may choose to provide an MCU that the kernel can consume for early loading. For example, Linux can apply an MCU very early in the kernel boot sequence. In situations where a BIOS update isn't available, early loading is the next best alternative to updating processor microcode. **Microcode states are reset on a power reset, hence its required that the MCU be loaded every time during boot process.**
+
+## Recommendation
+
+Using the initrd method to load an MCU is recommended as this method will load the MCU at the earliest time for the most coverage. Systems that cannot tolerate downtime may use the late-load method to update a running system without a reboot.
+
+## About Processor Signature, Family, Model, Stepping and Platform ID
+
+The Processor Signature is a number identifying the model and version of an Intel processor. It can be obtained using the *CPUID instruction*, via the command *lscpu*, or from the content of */proc/cpuinfo*. It's usually presented as 3 fields: Family, Model, and Stepping.
+
+For example, if a processor returns a value of "0x000906eb" from the *CPUID instruction*:
+
+| Reserved | Extended Family | Extended Model | Reserved | Processor Type | Family Code | Model Number | Stepping ID |
+|:---------|:----------------|:---------------|:---------|:---------------|:------------|:-------------|:------------|
+| 31:28 | 27:20 | 19:16 | 15:14 | 13:12 | 11:8 | 7:4 | 3:0 |
+| xxxx | 00000000b | 1001b | xx | 00b | 0110b | 1110b | 1011b |
+
+
+The corresponding Linux formatted file name will be "06-9e-0b", where:
+- Extended Family + Family = 0x06
+- Extended Model + Model Number = 0x9e
+- Stepping ID = 0xb
+
+A processor may be implemented for multiple platform types. Intel processors have a 3bit Platform ID field in MSR(17H) that specifies the platform type for up to 8 types. An MCU file for a specified processor model may support multiple platforms. The Platform ID(s) supported by an MCU is an 8bit mask where each set bit indicates a platform type that the MCU supports. The Platform ID of a processor can be read in Linux using rdmsr from [msr-tools](https://github.com/intel/msr-tools).
+
+## Microcode update instructions
+
+The [intel-ucode](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode) directory contains binary MCU files named in the `family-model-stepping` format. This file format is supported by most modern Linux distributions. It's generally located in the /lib/firmware directory and can be updated through the microcode reload interface following the late-load update instructions below.
+
+### Early-load update
+To update early loading initrd, consult your Linux distribution on how to package MCU files for early loading. Some distributions use `update-initramfs` or `dracut`. Use the OS vendors recommended method to help ensure that the MCU file is updated for early loading before attempting the late-load procedure below.
+
+### Late-load update
+To update the intel-ucode package to the system:
+1. Ensure the existence of `/sys/devices/system/cpu/microcode/reload`
+2. Download the latest microcode firmware</br> `$ git clone https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.git` or</br> `$ wget https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/main.zip`
+3. Copy `intel-ucode` directory to `/lib/firmware`, overwriting the files in /lib/firmware/intel-ucode/
+4. Write the reload interface to 1 to reload the microcode files, e.g.</br>
+ `$ echo 1 > /sys/devices/system/cpu/microcode/reload`</br>
+ Microcode updates will be applied automatically without rebooting the system.
+5. Update an existing initramfs so that next time it gets loaded via kernel:</br>
+`$ sudo update-initramfs -u`</br>
+`$ sudo reboot`
+6. Verify that the microcode was updated on boot or reloaded by echo command:</br>
+`$ dmesg | grep microcode` or</br>
+`$ cat /proc/cpuinfo | grep microcode | sort | uniq`
+
+If you are using the OS vendor method to apply an MCU, the above steps may have been done automatically during the update process.
+
+The [intel-ucode-with-caveats](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode-with-caveats) directory contains MCUs that need special handling. The BDX-ML MCU is provided in this directory because it requires special commits in the Linux kernel otherwise updating it might result in unexpected system behavior. OS vendors must ensure that the late loader patches (provided in [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches)) are included in the distribution before packaging the BDX-ML MCU for late-loading.
+
+The [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches) directory consists of kernel patches that address various issues related to applying MCUs.
+
+## Notes
+
+* You can only update to a higher MCU version (downgrade is not possible with the provided instructions)
+* To calculate Family-Model-Stepping, use Linux command:</br>
+`$ printf "%x\n" <number_to_convert_to_hex>`
+* There are multiple ways to check the MCU version number BEFORE update. After cloning this Intel Microcode update repo , run the following:
+ - `$ iucode_tool -l intel-ucode | grep -wF sig` ([iucode_tool](https://gitlab.com/iucode-tool/iucode-tool/-/wikis/home) package is required)
+ - `$ od -t x4 <Family-Model-Stepping>` will read the first 16 bytes of the microcode binary header specified in \<Family\-Model\-Stepping\>. The third block is the microcode version. For example:
+`$ od -t x4 06-55-04`</br>
+`0000000 00000001 *02000065* 09052019 00050654`
+
+## License
+
+See the [license](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/license) file for details.
+
+## Security Policy
+
+See the [security.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/security.md) file for details.
+
+## Release Note
+
+See the [releasenote.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) file for details.
+
+## Disclaimers
+
+Intel technologiesâ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at [www.intel.com](https://www.intel.com).
+
+No product or component can be absolutely secure.
+
+All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.
+
+The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request.
+
+Intel provides these materials as-is, with no express or implied warranties.
+
+© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
+
*Other names and brands may be claimed as the property of others.
\ No newline at end of file
diff --git a/changelog b/changelog
index da722c2..053875f 100644
--- a/changelog
+++ b/changelog
@@ -1,3 +1,166 @@
+2026-09-25:
+ * New upstream microcode datafile 20260925
+ * Updated microcode:
+ + sig 0x000a06a4, pf_mask 0xe6, 2026-09-03, rev 0x002b, size 141312
+
+2026-08-12:
+ * New upstream microcode datafile 20260812
+ * Downgraded MTL/06-aa-04/c0 to previously released version
+ due to functional issues observed when loading the MCU in
+ some platforms
+ * Downgraded microcodes:
+ + sig 0x000a06a4, pf_mask 0xe6, 2025-09-24, rev 0x0028, size 141312
+
+2026-08-11:
+ * New upstream microcode datafile 20260811
+ + Security updates for INTEL-SA-01379 (CVE-2025-31936)
+ + Security updates for INTEL-SA-01404 (CVE-2025-31938)
+ + Security updates for INTEL-SA-01423 (CVE-2026-20917)
+ + Security updates for INTEL-SA-01428 (CVE-2025-35973)
+ + Security updates for INTEL-SA-01435 (CVE-2026-20716)
+ + Security updates for INTEL-SA-01441 (CVE-2026-20760)
+ + Security updates for INTEL-SA-01442 (CVE-2026-20713, CVE-2026-20901)
+ + Security updates for INTEL-SA-01443 (CVE-2026-20707)
+ * Updated microcodes:
+ + sig 0x000606a6, pf_mask 0x87, 2026-03-09, rev 0xd000433, size 309248
+ + sig 0x000606c1, pf_mask 0x10, 2026-03-09, rev 0x1000301, size 301056
+ + sig 0x000706e5, pf_mask 0x80, 2026-02-12, rev 0x00ce, size 115712
+ + sig 0x000806f8, pf_mask 0x87, 2026-03-02, rev 0x2b000685, size 596992
+ + sig 0x000806f7, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f6, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f5, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f4, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f8, pf_mask 0x10, 2026-03-02, rev 0x2c000435, size 628736
+ + sig 0x000806f6, pf_mask 0x10, 2026-03-02, rev 0x2c000435
+ + sig 0x000806f5, pf_mask 0x10, 2026-03-02, rev 0x2c000435
+ + sig 0x000806f4, pf_mask 0x10, 2026-03-02, rev 0x2c000435
+ + sig 0x000a0671, pf_mask 0x02, 2026-02-12, rev 0x0066, size 109568
+ + sig 0x000a06d1, pf_mask 0x95, 2026-04-27, rev 0x1000434, size 1677312
+ + sig 0x000a06d1, pf_mask 0x20, 2026-03-24, rev 0xa000151, size 1647616
+ + sig 0x000a06a4, pf_mask 0xe6, 2026-02-20, rev 0x002a, size 141312
+ + sig 0x000a06e1, pf_mask 0x97, 2026-04-15, rev 0x1000309, size 1648640
+ + sig 0x000a06f3, pf_mask 0x01, 2026-03-16, rev 0x30003b2, size 1540096
+ + sig 0x000b0650, pf_mask 0x80, 2026-01-15, rev 0x000e, size 137216
+ + sig 0x000b0671, pf_mask 0x36, 2026-02-18, rev 0x0137, size 246784
+ + sig 0x000b0674, pf_mask 0x36, 2026-02-18, rev 0x0137
+ + sig 0x000d0670, pf_mask 0x36, 2026-02-18, rev 0x0137
+ + sig 0x000b06d1, pf_mask 0x80, 2026-02-19, rev 0x0128, size 81920
+ + sig 0x000c0662, pf_mask 0x82, 2026-02-18, rev 0x0122, size 91136
+ + sig 0x000c06a2, pf_mask 0x82, 2026-02-18, rev 0x0122
+ + sig 0x000c0652, pf_mask 0x82, 2026-02-18, rev 0x0122
+ + sig 0x000c0664, pf_mask 0x82, 2026-02-18, rev 0x0122
+ + sig 0x000c06c1, pf_mask 0x94, 2026-04-20, rev 0x011c, size 165888
+ + sig 0x000c06c2, pf_mask 0x94, 2026-04-20, rev 0x011c
+ + sig 0x000c06c3, pf_mask 0x94, 2026-04-20, rev 0x011c
+ + sig 0x000e0652, pf_mask 0x94, 2026-04-20, rev 0x011c
+ + sig 0x000c06f2, pf_mask 0x87, 2026-03-02, rev 0x210002f4, size 570368
+ + sig 0x000c06f2, pf_mask 0x87, 2026-03-02, rev 0x210002f4
+ + sig 0x000c06f1, pf_mask 0x87, 2026-03-02, rev 0x210002f4
+ * New microcodes:
+ + sig 0x000d0650, pf_mask 0xc0, 2026-05-20, rev 0x000c, size 84992
+ + sig 0x000d0651, pf_mask 0xc0, 2026-05-20, rev 0x000c
+ * New signatures:
+ + sig 0x000e0652, pf_mask 0x94, 2026-04-20, rev 0x011c, size 165888
+ + sig 0x000d0670, pf_mask 0x36, 2026-02-18, rev 0x0137, size 246784
+ + sig 0x000b0674, pf_mask 0x36, 2026-02-18, rev 0x0137, size 246784
+
+2026-05-12:
+ * New upstream microcode datafile 20260512
+ - mitigations for INTEL-SA-01420 (CVE-2025-35979)
+ Exposure of sensitive information caused by shared microarchitectural
+ predictor state that influences transient execution for some Intel
+ Processors within VMX non-root (guest) operation. Mitigations for
+ Intel Arrow Lake (Core Ultra 200S: sigs 0xc0652, 0xc0662), Lunar Lake
+ (Core Ultra series 2: sig 0xb06d1), and Panther Lake H
+ 4P+8E+4LP_E+12Xe (Core Ultra series 3: sig 0xc06c2)
+ - Fixes for undisclosed functional issues on several processors
+ * Updated microcodes:
+ + sig 0x000806f8, pf_mask 0x87, 2025-12-17, rev 0x2b000670, size 595968
+ + sig 0x000806f7, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000806f6, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000806f5, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000806f4, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000a06d1, pf_mask 0x95, 2026-01-29, rev 0x1000423, size 1671168
+ + sig 0x000a06d1, pf_mask 0x20, 2026-01-29, rev 0xa000142, size 1642496
+ + sig 0x000a06e1, pf_mask 0x97, 2026-02-26, rev 0x1000307, size 1646592
+ + sig 0x000a06f3, pf_mask 0x01, 2026-01-30, rev 0x30003a3, size 1533952
+ + sig 0x000b06d1, pf_mask 0x80, 2025-12-10, rev 0x0126, size 80896
+ + sig 0x000c0662, pf_mask 0x82, 2025-12-15, rev 0x0121, size 91136
+ + sig 0x000c06a2, pf_mask 0x82, 2025-12-15, rev 0x0121
+ + sig 0x000c0652, pf_mask 0x82, 2025-12-15, rev 0x0121
+ + sig 0x000c0664, pf_mask 0x82, 2025-12-15, rev 0x0121
+ + sig 0x000c06f2, pf_mask 0x87, 2025-12-17, rev 0x210002e0, size 567296
+ + sig 0x000c06f1, pf_mask 0x87, 2025-12-17, rev 0x210002e0
+ * New microcodes:
+ + sig 0x000c06c1, pf_mask 0x90, 2026-03-24, rev 0x011b, size 163840
+ + sig 0x000c06c2, pf_mask 0x90, 2026-03-24, rev 0x011b
+ + sig 0x000c06c3, pf_mask 0x90, 2026-03-24, rev 0x011b
+
+2026-02-27:
+ * New upstream microcode datafile 20260227
+ - Fixes functional issues on Intel Xeon 6700P-B/6500P-B SoC with P-Cores
+ * Updated microcodes:
+ + sig 0x000a06e1, pf_mask 0x97, 2025-12-02, rev 0x1000303, size 1645568
+
+2026-02-10:
+ * New upstream microcode datafile 20260210
+ - Updated mitigations for INTEL-SA-01083 (CVE-2024-24853)
+ Incorrect behavior order in transition between executive monitor and SMI
+ transfer monitor (STM) in some Intel Processors may allow a privileged
+ user to potentially enable escalation of privilege via local access.
+ - Mitigations for INTEL-SA-01396 (CVE-2025-31648)
+ Improper handling of values in the microcode flow for some Intel
+ Processor Family may allow an escalation of privilege. Startup code and
+ SMM adversary with a privileged user combined with a high complexity
+ attack may enable escalation of privilege via local access when attack
+ requirements are present, with low impact to the confidentiality and
+ integrity of the vulnerable system.
+ - Fixes for undisclosed functional issues on several processors
+ * Updated microcodes:
+ + sig 0x000606a6, pf_mask 0x87, 2025-08-19, rev 0xd000421, size 309248
+ + sig 0x000606c1, pf_mask 0x10, 2025-08-19, rev 0x10002f1, size 301056
+ + sig 0x000706e5, pf_mask 0x80, 2025-07-24, rev 0x00cc, size 115712
+ + sig 0x000806c1, pf_mask 0x80, 2025-07-24, rev 0x00be, size 112640
+ + sig 0x000806c2, pf_mask 0xc2, 2025-07-24, rev 0x003e, size 99328
+ + sig 0x000806d1, pf_mask 0xc2, 2025-07-24, rev 0x0058, size 105472
+ + sig 0x000806f8, pf_mask 0x87, 2025-08-25, rev 0x2b000661, size 595968
+ + sig 0x000806f7, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f6, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f5, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f4, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f8, pf_mask 0x10, 2025-08-25, rev 0x2c000421, size 626688
+ + sig 0x000806f8, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x000806f6, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x000806f5, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x000806f4, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x00090672, pf_mask 0x07, 2025-10-12, rev 0x003e, size 227328
+ + sig 0x00090675, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f2, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f5, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f6, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f7, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000906a3, pf_mask 0x80, 2025-10-12, rev 0x043b, size 225280
+ + sig 0x000906a4, pf_mask 0x80, 2025-10-12, rev 0x043b
+ + sig 0x000906a4, pf_mask 0x40, 2025-07-10, rev 0x000c, size 119808
+ + sig 0x000a0671, pf_mask 0x02, 2025-07-24, rev 0x0065, size 108544
+ + sig 0x000a06a4, pf_mask 0xe6, 2025-09-24, rev 0x0028, size 141312
+ + sig 0x000a06d1, pf_mask 0x95, 2025-10-31, rev 0x1000405, size 1672192
+ + sig 0x000a06d1, pf_mask 0x20, 2025-10-09, rev 0xa000133, size 1643520
+ + sig 0x000a06e1, pf_mask 0x97, 2025-11-03, rev 0x10002f3, size 1645568
+ + sig 0x000b0650, pf_mask 0x80, 2025-09-25, rev 0x000d, size 137216
+ + sig 0x000b0671, pf_mask 0x32, 2025-10-08, rev 0x0133, size 219136
+ + sig 0x000b0674, pf_mask 0x32, 2025-10-08, rev 0x0133
+ + sig 0x000b06a2, pf_mask 0xe0, 2025-10-08, rev 0x6134, size 224256
+ + sig 0x000b06a3, pf_mask 0xe0, 2025-10-08, rev 0x6134
+ + sig 0x000b06a8, pf_mask 0xe0, 2025-10-08, rev 0x6134
+ + sig 0x000b06e0, pf_mask 0x19, 2025-09-12, rev 0x0021, size 142336
+ + sig 0x000c0662, pf_mask 0x82, 2025-08-03, rev 0x011b, size 91136
+ + sig 0x000c06a2, pf_mask 0x82, 2025-08-03, rev 0x011b
+ + sig 0x000c0652, pf_mask 0x82, 2025-08-03, rev 0x011b
+ + sig 0x000c0664, pf_mask 0x82, 2025-08-03, rev 0x011b
+ + sig 0x000c06f2, pf_mask 0x87, 2025-08-25, rev 0x210002d3, size 566272
+ + sig 0x000c06f1, pf_mask 0x87, 2025-08-25, rev 0x210002d3
+
2025-11-11:
* New upstream microcode datafile 20251111
- Fixes for unspecified functional issues on several Intel, Intel
diff --git a/debian/changelog b/debian/changelog
index 52ff477..aa39587 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,201 @@
+intel-microcode (3.20260925.1~deb13u1) trixie; urgency=medium
+
+ * Upload to stable: no changes
+
+ -- Henrique de Moraes Holschuh <[email protected]> Wed, 04 Nov 2026 18:26:07 -0300
+
+intel-microcode (3.20260925.1) unstable; urgency=emergency
+
+ * New upstream microcode datafile 20260925 (closes: #1149038)
+ - Reinstates the mitigations for the security issues mentioned on
+ 3.20260811.1 for the Core Ultra Meteor Lake C0, sig 0xa06a4.
+ - Fix critical functional issue (fatal MCEs) on the Core Ultra Meteor Lake
+ C0 on some platforms (closes: #1152966)
+ * Updated microcodes:
+ + sig 0x000a06a4, pf_mask 0xe6, 2026-09-03, rev 0x002b, size 141312
+ * source: update symlinks to reflect id of the latest release, 20260925
+ * changelog: update for new upstream release
+ * debian/changelog: create entry for 3.20260812.1 (unreleased) to keep
+ upstream release information separate, given its security-related nature.
+
+ -- Henrique de Moraes Holschuh <[email protected]> Wed, 04 Nov 2026 14:26:43 -0300
+
+intel-microcode (3.20260812.1) UNRELEASED; urgency=high
+
+ * New upstream microcode datafile 20260812
+ - Revert the microcode update from 20260811 for the Core Ultra Meteor
+ Lake C0 to the previous release, due to severe functional issues on some
+ platforms. This effectively removes the security mitigations from release
+ 20260811 on this specific processor.
+ * Downgraded microcodes:
+ + sig 0x000a06a4, pf_mask 0xe6, 2025-09-24, rev 0x0028, size 141312
+ * New upstream microcode datafile 20260811 (closes: #1144154)
+ - Mitigation for several security issues: (closes: #1144158)
+ INTEL-SA-01379 (CVE-2025-31936), INTEL-SA-01404 (CVE-2025-31938),
+ INTEL-SA-01423 (CVE-2026-20917), INTEL-SA-01428 (CVE-2025-35973),
+ INTEL-SA-01435 (CVE-2026-20716), INTEL-SA-01441 (CVE-2026-20760),
+ INTEL-SA-01442 (CVE-2026-20713, CVE-2026-20901),
+ INTEL-SA-01443 (CVE-2026-20707)
+ - Fixes for undisclosed functional issues on several processors
+ * Updated microcodes:
+ + sig 0x000606a6, pf_mask 0x87, 2026-03-09, rev 0xd000433, size 309248
+ + sig 0x000606c1, pf_mask 0x10, 2026-03-09, rev 0x1000301, size 301056
+ + sig 0x000706e5, pf_mask 0x80, 2026-02-12, rev 0x00ce, size 115712
+ + sig 0x000806f8, pf_mask 0x87, 2026-03-02, rev 0x2b000685, size 596992
+ + sig 0x000806f7, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f6, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f5, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f4, pf_mask 0x87, 2026-03-02, rev 0x2b000685
+ + sig 0x000806f8, pf_mask 0x10, 2026-03-02, rev 0x2c000435, size 628736
+ + sig 0x000806f6, pf_mask 0x10, 2026-03-02, rev 0x2c000435
+ + sig 0x000806f5, pf_mask 0x10, 2026-03-02, rev 0x2c000435
+ + sig 0x000806f4, pf_mask 0x10, 2026-03-02, rev 0x2c000435
+ + sig 0x000a0671, pf_mask 0x02, 2026-02-12, rev 0x0066, size 109568
+ + sig 0x000a06d1, pf_mask 0x95, 2026-04-27, rev 0x1000434, size 1677312
+ + sig 0x000a06d1, pf_mask 0x20, 2026-03-24, rev 0xa000151, size 1647616
+ + sig 0x000a06e1, pf_mask 0x97, 2026-04-15, rev 0x1000309, size 1648640
+ + sig 0x000a06f3, pf_mask 0x01, 2026-03-16, rev 0x30003b2, size 1540096
+ + sig 0x000b0650, pf_mask 0x80, 2026-01-15, rev 0x000e, size 137216
+ + sig 0x000b0671, pf_mask 0x36, 2026-02-18, rev 0x0137, size 246784
+ + sig 0x000b0674, pf_mask 0x36, 2026-02-18, rev 0x0137
+ + sig 0x000d0670, pf_mask 0x36, 2026-02-18, rev 0x0137
+ + sig 0x000b06d1, pf_mask 0x80, 2026-02-19, rev 0x0128, size 81920
+ + sig 0x000c0662, pf_mask 0x82, 2026-02-18, rev 0x0122, size 91136
+ + sig 0x000c06a2, pf_mask 0x82, 2026-02-18, rev 0x0122
+ + sig 0x000c0652, pf_mask 0x82, 2026-02-18, rev 0x0122
+ + sig 0x000c0664, pf_mask 0x82, 2026-02-18, rev 0x0122
+ + sig 0x000c06c1, pf_mask 0x94, 2026-04-20, rev 0x011c, size 165888
+ + sig 0x000c06c2, pf_mask 0x94, 2026-04-20, rev 0x011c
+ + sig 0x000c06c3, pf_mask 0x94, 2026-04-20, rev 0x011c
+ + sig 0x000e0652, pf_mask 0x94, 2026-04-20, rev 0x011c
+ + sig 0x000c06f2, pf_mask 0x87, 2026-03-02, rev 0x210002f4, size 570368
+ + sig 0x000c06f2, pf_mask 0x87, 2026-03-02, rev 0x210002f4
+ + sig 0x000c06f1, pf_mask 0x87, 2026-03-02, rev 0x210002f4
+ * New microcodes:
+ + sig 0x000d0650, pf_mask 0xc0, 2026-05-20, rev 0x000c, size 84992
+ + sig 0x000d0651, pf_mask 0xc0, 2026-05-20, rev 0x000c
+ * New signatures:
+ + sig 0x000e0652, pf_mask 0x94, 2026-04-20, rev 0x011c, size 165888
+ + sig 0x000d0670, pf_mask 0x36, 2026-02-18, rev 0x0137, size 246784
+ + sig 0x000b0674, pf_mask 0x36, 2026-02-18, rev 0x0137, size 246784
+ * source: update symlinks to reflect id of the latest release, 20260812
+ * changelog: update for new upstream releases
+
+ -- Henrique de Moraes Holschuh <[email protected]> Tue, 03 Nov 2026 23:05:22 -0300
+
+intel-microcode (3.20260512.1) UNRELEASED; urgency=medium
+
+ * New upstream microcode datafile 20260512 (closes: #1137032, #1136460)
+ - mitigations for INTEL-SA-01420 (CVE-2025-35979)
+ Exposure of sensitive information caused by shared microarchitectural
+ predictor state that influences transient execution for some Intel
+ Processors within VMX non-root (guest) operation. Mitigations for
+ Intel Arrow Lake (Core Ultra 200S: sigs 0xc0652, 0xc0662), Lunar Lake
+ (Core Ultra series 2: sig 0xb06d1), and Panther Lake H
+ 4P+8E+4LP_E+12Xe (Core Ultra series 3: sig 0xc06c2)
+ - Fixes for undisclosed functional issues on several processors
+ * Updated microcodes:
+ + sig 0x000806f8, pf_mask 0x87, 2025-12-17, rev 0x2b000670, size 595968
+ + sig 0x000806f7, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000806f6, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000806f5, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000806f4, pf_mask 0x87, 2025-12-17, rev 0x2b000670
+ + sig 0x000a06d1, pf_mask 0x95, 2026-01-29, rev 0x1000423, size 1671168
+ + sig 0x000a06d1, pf_mask 0x20, 2026-01-29, rev 0xa000142, size 1642496
+ + sig 0x000a06e1, pf_mask 0x97, 2026-02-26, rev 0x1000307, size 1646592
+ + sig 0x000a06f3, pf_mask 0x01, 2026-01-30, rev 0x30003a3, size 1533952
+ + sig 0x000b06d1, pf_mask 0x80, 2025-12-10, rev 0x0126, size 80896
+ + sig 0x000c0662, pf_mask 0x82, 2025-12-15, rev 0x0121, size 91136
+ + sig 0x000c06a2, pf_mask 0x82, 2025-12-15, rev 0x0121
+ + sig 0x000c0652, pf_mask 0x82, 2025-12-15, rev 0x0121
+ + sig 0x000c0664, pf_mask 0x82, 2025-12-15, rev 0x0121
+ + sig 0x000c06f2, pf_mask 0x87, 2025-12-17, rev 0x210002e0, size 567296
+ + sig 0x000c06f1, pf_mask 0x87, 2025-12-17, rev 0x210002e0
+ * New microcodes:
+ + sig 0x000c06c1, pf_mask 0x90, 2026-03-24, rev 0x011b, size 163840
+ + sig 0x000c06c2, pf_mask 0x90, 2026-03-24, rev 0x011b
+ + sig 0x000c06c3, pf_mask 0x90, 2026-03-24, rev 0x011b
+ * debian/control: add dracut and tiny-initramfs as recommends
+ (closes: #1088079)
+ * debian/control: depend on linux-image-generic for autopkgtest on Ubuntu
+ * source: update symlinks to reflect id of the latest release, 20260512
+ * changelog: update for new upstream releases
+
+ -- Henrique de Moraes Holschuh <[email protected]> Sun, 24 May 2026 19:01:44 -0300
+
+intel-microcode (3.20260227.1) unstable; urgency=medium
+
+ * New upstream microcode datafile 20260227 (closes: #1129232)
+ - Fixes functional issues on Intel Xeon 6700P-B/6500P-B SoC with P-Cores
+ * Updated microcodes:
+ + sig 0x000a06e1, pf_mask 0x97, 2025-12-02, rev 0x1000303, size 1645568
+ * source: update symlinks to reflect id of the latest release, 20260227
+ * debian/rules: enforce LF end-of-line markers when installing upstream docs
+
+ -- Henrique de Moraes Holschuh <[email protected]> Sat, 07 Mar 2026 11:55:42 -0300
+
+intel-microcode (3.20260210.1) unstable; urgency=medium
+
+ * New upstream microcode datafile 20260210 (closes: #1127837)
+ - Updated mitigations for INTEL-SA-01083 (CVE-2024-24853)
+ Incorrect behavior order in transition between executive monitor and SMI
+ transfer monitor (STM) in some Intel Processors may allow a privileged
+ user to potentially enable escalation of privilege via local access.
+ - Mitigations for INTEL-SA-01396 (CVE-2025-31648)
+ Improper handling of values in the microcode flow for some Intel
+ Processor Family may allow an escalation of privilege. Startup code and
+ SMM adversary with a privileged user combined with a high complexity
+ attack may enable escalation of privilege via local access when attack
+ requirements are present, with low impact to the confidentiality and
+ integrity of the vulnerable system.
+ - Fixes for undisclosed functional issues on several processors
+ * Updated microcodes:
+ + sig 0x000606a6, pf_mask 0x87, 2025-08-19, rev 0xd000421, size 309248
+ + sig 0x000606c1, pf_mask 0x10, 2025-08-19, rev 0x10002f1, size 301056
+ + sig 0x000706e5, pf_mask 0x80, 2025-07-24, rev 0x00cc, size 115712
+ + sig 0x000806c1, pf_mask 0x80, 2025-07-24, rev 0x00be, size 112640
+ + sig 0x000806c2, pf_mask 0xc2, 2025-07-24, rev 0x003e, size 99328
+ + sig 0x000806d1, pf_mask 0xc2, 2025-07-24, rev 0x0058, size 105472
+ + sig 0x000806f8, pf_mask 0x87, 2025-08-25, rev 0x2b000661, size 595968
+ + sig 0x000806f7, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f6, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f5, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f4, pf_mask 0x87, 2025-08-25, rev 0x2b000661
+ + sig 0x000806f8, pf_mask 0x10, 2025-08-25, rev 0x2c000421, size 626688
+ + sig 0x000806f8, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x000806f6, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x000806f5, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x000806f4, pf_mask 0x10, 2025-08-25, rev 0x2c000421
+ + sig 0x00090672, pf_mask 0x07, 2025-10-12, rev 0x003e, size 227328
+ + sig 0x00090675, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f2, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f5, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f6, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000b06f7, pf_mask 0x07, 2025-10-12, rev 0x003e
+ + sig 0x000906a3, pf_mask 0x80, 2025-10-12, rev 0x043b, size 225280
+ + sig 0x000906a4, pf_mask 0x80, 2025-10-12, rev 0x043b
+ + sig 0x000906a4, pf_mask 0x40, 2025-07-10, rev 0x000c, size 119808
+ + sig 0x000a0671, pf_mask 0x02, 2025-07-24, rev 0x0065, size 108544
+ + sig 0x000a06a4, pf_mask 0xe6, 2025-09-24, rev 0x0028, size 141312
+ + sig 0x000a06d1, pf_mask 0x95, 2025-10-31, rev 0x1000405, size 1672192
+ + sig 0x000a06d1, pf_mask 0x20, 2025-10-09, rev 0xa000133, size 1643520
+ + sig 0x000a06e1, pf_mask 0x97, 2025-11-03, rev 0x10002f3, size 1645568
+ + sig 0x000b0650, pf_mask 0x80, 2025-09-25, rev 0x000d, size 137216
+ + sig 0x000b0671, pf_mask 0x32, 2025-10-08, rev 0x0133, size 219136
+ + sig 0x000b0674, pf_mask 0x32, 2025-10-08, rev 0x0133
+ + sig 0x000b06a2, pf_mask 0xe0, 2025-10-08, rev 0x6134, size 224256
+ + sig 0x000b06a3, pf_mask 0xe0, 2025-10-08, rev 0x6134
+ + sig 0x000b06a8, pf_mask 0xe0, 2025-10-08, rev 0x6134
+ + sig 0x000b06e0, pf_mask 0x19, 2025-09-12, rev 0x0021, size 142336
+ + sig 0x000c0662, pf_mask 0x82, 2025-08-03, rev 0x011b, size 91136
+ + sig 0x000c06a2, pf_mask 0x82, 2025-08-03, rev 0x011b
+ + sig 0x000c0652, pf_mask 0x82, 2025-08-03, rev 0x011b
+ + sig 0x000c0664, pf_mask 0x82, 2025-08-03, rev 0x011b
+ + sig 0x000c06f2, pf_mask 0x87, 2025-08-25, rev 0x210002d3, size 566272
+ + sig 0x000c06f1, pf_mask 0x87, 2025-08-25, rev 0x210002d3
+
+ -- Henrique de Moraes Holschuh <[email protected]> Sat, 14 Feb 2026 09:13:55 -0300
+
intel-microcode (3.20251111.1~deb13u1) trixie; urgency=medium
* Upload to stable: no changes
diff --git a/debian/control b/debian/control
index 86659b3..a6e4c41 100644
--- a/debian/control
+++ b/debian/control
@@ -13,7 +13,7 @@ XS-Autobuild: yes
Package: intel-microcode
Architecture: i386 amd64 x32
Depends: ${misc:Depends}, iucode-tool (>= 1.0)
-Recommends: initramfs-tools (>= 0.113~)
+Recommends: initramfs-tools (>= 0.113~) | dracut (>= 044~) | tiny-initramfs
Conflicts: microcode.ctl (<< 0.18~0)
Description: Processor microcode firmware for Intel CPUs
This package contains updated system processor microcode for
diff --git a/debian/rules b/debian/rules
index 716614f..c776e26 100755
--- a/debian/rules
+++ b/debian/rules
@@ -62,3 +62,7 @@ override_dh_auto_install:
override_dh_installchangelogs:
dh_installchangelogs changelog
+override_dh_installdocs:
+ dh_installdocs
+ (cd "$(DEBDIR)/$(PACKAGE)/usr/share/doc/$(PACKAGE)/" && sed -i -E 's/\r//g' *.md)
+
diff --git a/debian/tests/control b/debian/tests/control
index a5d82d6..3a9458b 100644
--- a/debian/tests/control
+++ b/debian/tests/control
@@ -2,6 +2,6 @@ Tests: initramfs
Architecture: amd64
Depends:
@,
- linux-image-amd64,
+ linux-image-generic,
initramfs-tools,
Restrictions: needs-root, allow-stderr, superficial
diff --git a/debian/tests/initramfs b/debian/tests/initramfs
index 32c8bc4..edecab5 100644
--- a/debian/tests/initramfs
+++ b/debian/tests/initramfs
@@ -1,7 +1,7 @@
#!/bin/bash
set -ex -o pipefail
-update-initramfs -kall -u
+update-initramfs -kall -u -c
INITRDS=(/boot/initrd.img-*)
unmkinitramfs "${INITRDS[0]}" initramfs/
diff --git a/intel-ucode/06-6a-06 b/intel-ucode/06-6a-06
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diff --git a/intel-ucode/06-cc-02 b/intel-ucode/06-cc-02
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index 98dc450..becec6b 100644
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new file mode 100644
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diff --git a/intel-ucode/06-d7-00 b/intel-ucode/06-d7-00
new file mode 100644
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diff --git a/microcode-20251111.d b/microcode-20260925.d
similarity index 100%
rename from microcode-20251111.d
rename to microcode-20260925.d
diff --git a/releasenote.md b/releasenote.md
index a65ad7d..b6b8ec4 100644
--- a/releasenote.md
+++ b/releasenote.md
@@ -1,3 +1,206 @@
+# Release Notes
+## [microcode-20260925](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260925)
+
+### Purpose
+
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processor](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details.
+
+### Updated Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| MTL | C0 | 06-aa-04/e6 | 00000028 | 0000002b | Core Ultra Processor
+
+
+# Release Notes
+## [microcode-20260812](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260812)
+
+### Purpose
+
+- Removed MTL/06-aa-04/c0 due to functional issues observed when loading the MCU in some platforms.
+
+
+# Release Notes
+## [microcode-20260811](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260811)
+
+### Purpose
+- Security updates for [INTEL-SA-01379](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01379.html)
+- Security updates for [INTEL-SA-01404](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01404.html)
+- Security updates for [INTEL-SA-01423](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01423.html)
+- Security updates for [INTEL-SA-01428](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01428.html)
+- Security updates for [INTEL-SA-01435](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01435.html)
+- Security updates for [INTEL-SA-01441](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01441.html)
+- Security updates for [INTEL-SA-01442](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01442.html)
+- Security updates for [INTEL-SA-01443](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01443.html)
+- Update for functional issues. Refer to [10th Gen Intel® Core⢠Processor Families Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/341079) for details.
+- Update for functional issues. Refer to [13th/14th Gen Intel® Core⢠Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details.
+- Update for functional issues. Refer to [3rd Generation Intel® Xeon® Processor Scalable Family Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/637780) for details.
+- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details.
+- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details.
+- Update for functional issues. Refer to Intel ®Core Series 2 Processors with P-cores for details.
+- Update for functional issues. Refer to [Intel® Core⢠Processors (Series 3)](https://cdrdv2.intel.com/v1/dl/getContent/914196) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra 200 V Series Processor](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processor (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processor](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processors (Series 3)](https://cdrdv2.intel.com/v1/dl/getContent/869992) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6700 Series Processors with E-cores](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details.
+- Update for functional issues. Refer to [Intel® Xeon® D-2700 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/714071) for details.
+- Update for functional issues. Refer to [Intel® Xeon® E-2300 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/709192) for details.
+
+### New Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| BTL-S12P | A0 | 06-d7-00/36 | | 00000137 | Intel Core Series 2 Processors with P-cores
+| BTL-S816 | B0 | 06-b7-04/36 | | 00000137 | Intel Core Series 2 Processors with P-cores
+| WCL | A1 | 06-d5-01/c0 | | 0000000c | Intel Core Processors (Series 3)
+
+
+### Updated Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| ARL-H | A1 | 06-c5-02/82 | 00000121 | 00000122 | Core Ultra Processor (Series 2)
+| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 00000121 | 00000122 | Core Ultra Processor (Series 2)
+| ARL-U | A0 | 06-b5-00/80 | 0000000d | 0000000e | Core Ultra Processor (Series 2)
+| EMR-SP | A1 | 06-cf-02/87 | 210002e0 | 210002f4 | Xeon Scalable Gen5
+| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 01000423 | 01000434 | Xeon 6900/6700/6500 Series Processors with P-Cores
+| GNR-D | B0/B1 | 06-ae-01/97 | 01000307 | 01000309 | Xeon 6700P-B/6500P-B Series SoC with P-Cores
+| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000142 | 0a000151 | Xeon 6700/6500-Series Processors with P-Cores
+| ICL-D | B0 | 06-6c-01/10 | 010002f1 | 01000301 | Xeon D-17xx, D-27xx
+| ICL-U/Y | D1 | 06-7e-05/80 | 000000cc | 000000ce | Core Gen10 Mobile
+| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d000421 | 0d000433 | Xeon Scalable Gen3
+| LNL | B0 | 06-bd-01/80 | 00000126 | 00000128 | Core Ultra 200 V Series Processor
+| MTL | C0 | 06-aa-04/e6 | 00000028 | 0000002a | Core Ultra Processor
+| PTL-404/H204 | A1 | 06-cc-03/94 | 0000011b | 0000011c | Intel Core Ultra processor (Series 3)
+| PTL-H484/PTL-H12Xe | B0/A0| 06-cc-02/94 | 0000011b | 0000011c | Intel Core Ultra processor (Series 3)
+| RKL-S | B0 | 06-a7-01/02 | 00000065 | 00000066 | Core Gen11
+| RPL-E/HX/S | B0 | 06-b7-01/36 | 00000133 | 00000137 | Core Gen13/Gen14
+| SPR-HBM | Bx | 06-8f-08/10 | 2c000421 | 2c000435 | Xeon Max
+| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000670 | 2b000685 | Xeon Scalable Gen4
+| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000670 | 2b000685 | Xeon Scalable Gen4
+| SRF-AP/SP | C0 | 06-af-03/01 | 030003a3 | 030003b2 | Xeon 6900/6700-Series Processors with E-Cores
+
+
+# Release Notes
+## [microcode-20260512](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260512)
+
+### Purpose
+
+- Security updates for [INTEL-SA-01420](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01420.html)
+- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details.
+- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra 200 V Series Processor](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processors (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processors (Series 3)](https://cdrdv2.intel.com/v1/dl/getContent/869992) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6700 Series Processors with E-cores](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306) for details.
+
+### New Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| PTL 404 | A1 | 06-cc-03/90 | | 0000011b | Intel Core Ultra Processor (Series 3)
+| PTL-H 484/12Xe | A0/B0 | 06-cc-02/90 | | 0000011b | Intel Core Ultra Processor (Series 3)
+
+### Updated Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| ARL-H | A1 | 06-c5-02/82 | 0000011b | 00000121 | Core Ultra Processor (Series 2)
+| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 0000011b | 00000121 | Core Ultra Processor (Series 2)
+| EMR-SP | A1 | 06-cf-02/87 | 210002d3 | 210002e0 | Xeon Scalable Gen5
+| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 01000405 | 01000423 | Xeon 6900/6700/6500 Series Processors with P-Cores
+| GNR-D | B0/B1 | 06-ae-01/97 | 01000303 | 01000307 | Xeon 6700P-B/6500P-B Series SoC with P-Cores
+| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000133 | 0a000142 | Xeon 6700/6500-Series Processors with P-Cores
+| LNL | B0 | 06-bd-01/80 | 00000125 | 00000126 | Core Ultra 200 V Series Processor
+| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000661 | 2b000670 | Xeon Scalable Gen4
+| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000661 | 2b000670 | Xeon Scalable Gen4
+| SRF-AP/SP | C0 | 06-af-03/01 | 03000382 | 030003a3 | Xeon 6900/6700-Series Processors with E-Cores
+
+
+# Release Notes
+## [microcode-20260227](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260227)
+
+### Purpose
+- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306/view?wapkw=intel%20xeon%206700P-B) for details.
+
+
+### Updated Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| GNR-D | B0/B1 | 06-ae-01/97 | 010002f3 | 01000303 | Xeon 6700P-B/6500P-B Series SoC with P-Cores
+
+
+# Release Notes
+## [microcode-20260210](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260210)
+
+### Purpose
+- Updated security updates for INTEL-SA-01083 originally published on Aug 13, 2024 [INTEL-SA-01083](https://www.intel.com/content/www/us/en/security-center/advisory/INTEL-SA-01083.html)
+- Security updates for [INTEL-SA-01396](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01396.html)
+- Update for functional issues. Refer to [10th Gen Intel® Core⢠Processor Families Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/341079) for details.
+- Update for functional issues. Refer to [11th Gen Intel® Core⢠Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/631123) for details.
+- Update for functional issues. Refer to [12th Generation Intel® Core⢠Processor Family](https://cdrdv2.intel.com/v1/dl/getContent/682436) for details.
+- Update for functional issues. Refer to [13th Generation Intel® Core⢠Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details.
+- Update for functional issues. Refer to [13th/14th Gen Intel® Core⢠Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details.
+- Update for functional issues. Refer to [3rd Generation Intel® Xeon® Processor Scalable Family Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/637780) for details.
+- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update ](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details.
+- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processor ](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details.
+- Update for functional issues. Refer to [Intel® Core⢠Ultra Processor (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774?explicitVersion=true?) for details.
+- Update for functional issues. Refer to [Intel® Processors and Intel® Core⢠i3 N-Series](https://cdrdv2.intel.com/v1/dl/getContent/764616) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details.
+- Update for functional issues. Refer to [Intel® Xeon® D-2700 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/714071) for details.
+- Update for functional issues. Refer to [Intel® Xeon® E-2300 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/709192) for details.
+- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306/view?wapkw=intel%20xeon%206700P-B) for details.
+
+
+### New Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+
+
+### Updated Platforms
+
+| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| ADL | C0 | 06-97-02/07 | 0000003d | 0000003e | Core Gen12
+| ADL | H0 | 06-97-05/07 | 0000003d | 0000003e | Core Gen12
+| ADL | L0 | 06-9a-03/80 | 0000043a | 0000043b | Core Gen12
+| ADL | R0 | 06-9a-04/80 | 0000043a | 0000043b | Core Gen12
+| ADL-N | N0 | 06-be-00/19 | 0000001e | 00000021 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
+| ARL-H | A1 | 06-c5-02/82 | 0000011a | 0000011b | Core Ultra Processor (Series 2)
+| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 0000011a | 0000011b | Core Ultra Processor (Series 2)
+| ARL-U | A0 | 06-b5-00/80 | 0000000a | 0000000d | Core Ultra Processor (Series 2)
+| AZB | A0/R0 | 06-9a-04/40 | 0000000b | 0000000c | Atom C1100
+| EMR-SP | A1 | 06-cf-02/87 | 210002c0 | 210002d3 | Xeon Scalable Gen5
+| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 010003f0 | 01000405 | Xeon 6900/6700/6500 Series Processors with P-Cores
+| GNR-D | B0/B1 | 06-ae-01/97 | 01000273 | 010002f3 | Xeon 6700P-B/6500P-B Series SoC with P-Cores
+| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000124 | 0a000133 | Xeon 6700/6500-Series Processors with P-Cores
+| ICL-D | B0 | 06-6c-01/10 | 010002e0 | 010002f1 | Xeon D-17xx, D-27xx
+| ICL-U/Y | D1 | 06-7e-05/80 | 000000ca | 000000cc | Core Gen10 Mobile
+| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d000410 | 0d000421 | Xeon Scalable Gen3
+| MTL | C0 | 06-aa-04/e6 | 00000025 | 00000028 | Core⢠Ultra Processor
+| RKL-S | B0 | 06-a7-01/02 | 00000064 | 00000065 | Core Gen11
+| RPL-E/HX/S | B0 | 06-b7-01/32 | 00000132 | 00000133 | Core Gen13/Gen14
+| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00006133 | 00006134 | Core Gen13
+| RPL-HX/S | C0 | 06-bf-02/07 | 0000003d | 0000003e | Core Gen13/Gen14
+| RPL-S | H0 | 06-bf-05/07 | 0000003d | 0000003e | Core Gen13/Gen14
+| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00006133 | 00006134 | Core Gen13
+| SPR-HBM | Bx | 06-8f-08/10 | 2c000410 | 2c000421 | Xeon Max
+| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000650 | 2b000661 | Xeon Scalable Gen4
+| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000650 | 2b000661 | Xeon Scalable Gen4
+| TGL | B0/B1 | 06-8c-01/80 | 000000bc | 000000be | Core Gen11 Mobile
+| TGL-H | R0 | 06-8d-01/c2 | 00000056 | 00000058 | Core Gen11 Mobile
+| TGL-R | C0 | 06-8c-02/c2 | 0000003c | 0000003e | Core Gen11 Mobile
+| TWL | N0 | 06-be-00/19 | 0000001e | 00000021 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
+
+
# Release Notes
## [microcode-20251111](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20251111)
diff --git a/security.md b/security.md
index 3193a4d..c39feb7 100644
--- a/security.md
+++ b/security.md
@@ -1,39 +1,39 @@
-# Security Policy
-
-## Report a Vulnerability
-
-If you have information about a security issue or vulnerability with an **Intel branded product or technology**, please send an e-mail to [[email protected]](mailto:[email protected]). Encrypt sensitive information using our [PGP public key](https://www.intel.com/content/www/us/en/security-center/pgp-public-key.html).
-
-Please provide as much information as possible, including:
-
-- The products and versions affected
-- Detailed description of the vulnerability
-- Information on known exploits
-
-A member of the Intel Product Security Team will review your e-mail and contact you to collaborate on resolving the issue. For more information on how Intel works to resolve security issues, see:
-
-- [Vulnerability handling guidelines](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html)
-
-For issues related to Intel's external web presence (Intel.com and related subdomains), please contact [Intel's External Security Research team](mailto:[email protected]).
-
-## Intel's Bug Bounty Program
-
-Intel Corporation believes that working with skilled security researchers across the globe is a crucial part of identifying and mitigating security vulnerabilities in Intel products.
-
-Like other major technology companies, Intel incentivizes security researchers to report security vulnerabilities in Intel products to us to enable a coordinated response. To encourage closer collaboration with the security research community on these kinds of issues, Intel created its Bug Bounty Program.
-
-If you believe you've found a security vulnerability in an Intel product or technology, we encourage you to notify us through our program and work with us to mitigate and to coordinate disclosure of the vulnerability.
-
-[Read full details.](https://www.intel.com/content/www/us/en/security-center/bug-bounty-program.html)
-
-## Need product support?
-
-The [[email protected]](mailto:[email protected]) e-mail address should only be used for reporting security issues.
-
-If you...
-
-- Have questions about the security features of an Intel product
-- Require technical support
-- Want product updates or patches
-
-Please visit [Support & Downloads](https://www.intel.com/content/www/us/en/support.html).
+# Security Policy
+
+## Report a Vulnerability
+
+If you have information about a security issue or vulnerability with an **Intel branded product or technology**, please send an e-mail to [[email protected]](mailto:[email protected]). Encrypt sensitive information using our [PGP public key](https://www.intel.com/content/www/us/en/security-center/pgp-public-key.html).
+
+Please provide as much information as possible, including:
+
+- The products and versions affected
+- Detailed description of the vulnerability
+- Information on known exploits
+
+A member of the Intel Product Security Team will review your e-mail and contact you to collaborate on resolving the issue. For more information on how Intel works to resolve security issues, see:
+
+- [Vulnerability handling guidelines](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html)
+
+For issues related to Intel's external web presence (Intel.com and related subdomains), please contact [Intel's External Security Research team](mailto:[email protected]).
+
+## Intel's Bug Bounty Program
+
+Intel Corporation believes that working with skilled security researchers across the globe is a crucial part of identifying and mitigating security vulnerabilities in Intel products.
+
+Like other major technology companies, Intel incentivizes security researchers to report security vulnerabilities in Intel products to us to enable a coordinated response. To encourage closer collaboration with the security research community on these kinds of issues, Intel created its Bug Bounty Program.
+
+If you believe you've found a security vulnerability in an Intel product or technology, we encourage you to notify us through our program and work with us to mitigate and to coordinate disclosure of the vulnerability.
+
+[Read full details.](https://www.intel.com/content/www/us/en/security-center/bug-bounty-program.html)
+
+## Need product support?
+
+The [[email protected]](mailto:[email protected]) e-mail address should only be used for reporting security issues.
+
+If you...
+
+- Have questions about the security features of an Intel product
+- Require technical support
+- Want product updates or patches
+
+Please visit [Support & Downloads](https://www.intel.com/content/www/us/en/support.html).
diff --git a/supplementary-ucode-20251111_BDX-ML.bin b/supplementary-ucode-20260925_BDX-ML.bin
similarity index 100%
rename from supplementary-ucode-20251111_BDX-ML.bin
rename to supplementary-ucode-20260925_BDX-ML.bin
README.md | 210 ++++++++++++++++++++++++-------------------------
changelog | 163 ++++++++++++++++++++++++++++++++++++++
debian/changelog | 198 ++++++++++++++++++++++++++++++++++++++++++++++
debian/control | 2
debian/rules | 4
debian/tests/control | 2
debian/tests/initramfs | 2
intel-ucode/06-6a-06 |binary
intel-ucode/06-6c-01 |binary
intel-ucode/06-7e-05 |binary
intel-ucode/06-8c-01 |binary
intel-ucode/06-8c-02 |binary
intel-ucode/06-8d-01 |binary
intel-ucode/06-8f-07 |binary
intel-ucode/06-8f-08 |binary
intel-ucode/06-97-02 |binary
intel-ucode/06-97-05 |binary
intel-ucode/06-9a-03 |binary
intel-ucode/06-9a-04 |binary
intel-ucode/06-a7-01 |binary
intel-ucode/06-aa-04 |binary
intel-ucode/06-ad-01 |binary
intel-ucode/06-ae-01 |binary
intel-ucode/06-af-03 |binary
intel-ucode/06-b5-00 |binary
intel-ucode/06-b7-01 |binary
intel-ucode/06-b7-04 |binary
intel-ucode/06-ba-02 |binary
intel-ucode/06-ba-03 |binary
intel-ucode/06-bd-01 |binary
intel-ucode/06-be-00 |binary
intel-ucode/06-bf-02 |binary
intel-ucode/06-bf-05 |binary
intel-ucode/06-c5-02 |binary
intel-ucode/06-c6-02 |binary
intel-ucode/06-cc-02 |binary
intel-ucode/06-cc-03 |binary
intel-ucode/06-cf-02 |binary
intel-ucode/06-d5-01 |binary
intel-ucode/06-d7-00 |binary
releasenote.md | 203 +++++++++++++++++++++++++++++++++++++++++++++++
security.md | 78 +++++++++---------
42 files changed, 715 insertions(+), 147 deletions(-)
