Jurij Smakov wrote:
The offending instruction tries to load a 4-byte word located at
address %l0 into %g1 register, so it's expected to be aligned on a
4-byte boundary, however it is obviously not:
(gdb) info reg l0
l0 0xf581f42e -176032722
(gdb)
Figuring out why this happens is the tricky part :-).
Noting that Peter is active in the debian-arm mailing list, I think it's
worth remarking that at least some ARM variants are sensitive to the
same alignment issues as SPARC. I've hassled the FPC developers a lot
over this, and in general a fix that was good for one architecture
turned out to be good for the others.
--
Mark Morgan Lloyd
markMLl .AT. telemetry.co .DOT. uk
[Opinions above are the author's, not those of his employers or colleagues]
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